MAX1280 Datasheet, PDF (15/24 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
SCLK
t_CSS
t_CSO
DIN
t_DOE
DOUT
t_STE
SSTRB
t_CH
t_CL
t_DS
t_DH
t_CP
t_DOH
t_DOV
t_STH
t_STV
t_CSW
t_CSH
t_CS1
t_DOD
t_STD
Figure 7. Detailed Serial-Interface Timing
Serial Clock
The external serial clock not only shifts data in and out,
but also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the next
12 SCLK falling edges (Figure 6). SSTRB and DOUT go
into a high-impedance state when CS goes high; after
the next CS rising edge, SSTRB outputs a logic low.
Figure 7 shows the detailed serial-interface timing.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge after the eighth bit of
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V_DD1 and V_DD2
are applied.
OR
The first high bit clocked into DIN after bit 6 of a con-
version in progress is clocked onto the DOUT pin.
Once a start bit has been recognized, the current con-
version may only be terminated by pulling SHDN low.
The fastest the MAX1280/MAX1281 can run with CS
held low between conversions is 16 clocks per conver-
sion. Figure 8 shows the serial-interface timing neces-
sary to perform a conversion every 16 SCLK cycles. If
CS is tied low and SCLK is continuous, guarantee a
start bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1280/MAX1281 in normal operating mode, ready to
convert with SSTRB = low. The MAX1280/MAX1281
require 10µs to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logic 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.
Power Modes
You can save power by placing the converter in one of
the two low-current operating modes or in full power-
down between conversions. Select the power mode
through bit 1 and bit 0 of the DIN control byte (Tables 1
and 4), or force the converter into hardware shutdown
by driving SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
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