MAX1280 Datasheet, PDF (17/24 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 4 details the four power modes with the corre-
sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1280/MAX1281 can be considered fully
powered-up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time depends on the external bypass
capacitors and shutdown duration.
Power-Down Sequencing
The MAX1280/MAX1281’s automatic power-down
modes can save considerable power when operating at
1.50
1.25
1.00
0.75
0.50
0.25
0
0.0001 0.001 0.01 0.1
1
10
TIME IN SHUTDOWN (s)
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
1000
MAX1281
V_DD1 = V_DD2 = 3.0V
C_LOAD = 20pF
CODE = 101010000000
100
8 CHANNELS
10
1 CHANNEL
less than maximum sample rates. Figures 10 and 11
show the average supply current as a function of the
sampling rate.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption at up to 1000 conversions per
channel per second. Figure 10a shows the MAX1281’s
power consumption for 1- or 8-channel conversions
using full power-down mode (PD1 = PD0 = 0), with the
internal reference and the maximum clock speed. A
0.01µF bypass capacitor plus the internal 17kΩ refer-
ence resistor at REFADJ forms an RC filter with a 200µs
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up if the
bypass capacitor is fully discharged between conver-
sions. Waiting this 2ms in FASTPD mode or reduced-
power mode (REDP) instead of full power-down mode
can further reduce power consumption. This is
achieved by using the sequence shown in Figure 12a.
Figure 10b shows the MAX1281’s power consumption
for 1- or 8-channel conversions using FULLPD mode
(PD1 = PD0 = 0), an external reference, and the maxi-
mum clock speed. One dummy conversion to power-up
the device is needed, but no wait-time is necessary to
start the second conversion, thereby achieving lower
power consumption at up to the full sampling rate.
Using Fast Power-Down and
Reduced-Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sample
rate. Figure 11 shows the MAX1281’s power consump-
tion in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode
(PD1 = 1, PD0 = 0), and (for comparison) normal
operating mode (PD = 1, PD0 = 1). The figure shows
10,000
1000
MAX1281
V_DD1 = V_DD2 = 3.0V
C_LOAD = 20pF
CODE = 101010000000
8 CHANNELS
100
1 CHANNEL
10
1
0.1
1
10
100
1k
10k
SAMPLING RATE (sps)
Figure 10a. Average Supply Current vs. Sample Rate (Using
FULLPD and Internal Reference)
1
1
10 100 1k 10k 100k
SAMPLING RATE (sps)
Figure 10b. Average Supply Current vs. Sampling Rate (Using
FULLPD and External Reference)
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