MAX12553 Datasheet, PDF (13/28 Pages) Maxim Integrated Products – 14-Bit, 65Msps, 3.3V ADC

14-Bit, 65Msps, 3.3V ADC
Pin Description (continued)
PIN
NAME
FUNCTION
28
D4
CMOS Digital Output, Bit 4
29
D3
CMOS Digital Output, Bit 3
30
D2
CMOS Digital Output, Bit 2
31
D1
CMOS Digital Output, Bit 1
32
D0
CMOS Digital Output, Bit 0 (LSB)
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
33
DAV
any input clock duty-cycle variations. DAV is typically used to latch the MAX12553 output data into an
external back-end digital circuit.
37
PD
Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
38
REFOUT or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
39
REFIN GND with a ≥0.1µF capacitor. In these modes,V_REFP - V_REFN = V_REFIN x 3/4. For unbuffered external
reference mode operation, connect REFIN to GND.
40
G/T
Output Format Select Input. Connect G/T to GND for the two’s complement digital output format.
Connect G/T to OV_DD or V_DD for the Gray code digital output format.
Exposed Paddle. The MAX12553 relies on the exposed paddle connection for a low-inductance ground
—
EP
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
MAX12553
T/H
FLASH
ADC
+
Σ
−
DAC
INP
T/H
STAGE 1
INN
STAGE 2
STAGE 9
STAGE 10
END OF PIPE
DIGITAL ERROR CORRECTION
D13–D0
OUTPUT
DRIVERS
D13–D0
Figure 1. Pipeline Architecture—Stage Blocks
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