MAX12553 Datasheet, PDF (12/28 Pages) Maxim Integrated Products – 14-Bit, 65Msps, 3.3V ADC

14-Bit, 65Msps, 3.3V ADC
PIN
1
2
3
4, 7, 16,
35
5
6
8
9
10
11
12–15, 36
17, 34
18
19
20
21
22
23
24
25
26
27
NAME
REFP
REFN
COM
GND
INP
INN
DCE
CLKN
CLKP
CLKTYP
V_DD
OV_DD
DOR
D13
D12
D11
D10
D9
D8
D7
D6
D5
Pin Description
FUNCTION
Positive Reference I/O. The full-scale analog input range is ±(V_REFP - V_REFN) x 2/3. Bypass REFP to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
Negative Reference I/O. The full-scale analog input range is ±(V_REFP - V_REFN) x 2/3. Bypass REFN to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX12553 through a via.
Ground. Connect all ground pins and EP together.
Positive Analog Input
Negative Analog Input
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OV_DD or V_DD) to enable the internal duty-cycle equalizer.
Negative Clock Input. In differential clock input mode (CLKTYP = OV_DD or V_DD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
Positive Clock Input. In differential clock input mode (CLKTYP = OV_DD or V_DD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OV_DD or V_DD to define the differential clock input.
Analog Power Input. Connect V_DD to a 3.15V to 3.60V power supply. Bypass V_DD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all V_DD pins to the same potential.
Output-Driver Power Input. Connect OV_DD to a 1.7V to V_DD power supply. Bypass OV_DD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).
CMOS Digital Output, Bit 13 (MSB)
CMOS Digital Output, Bit 12
CMOS Digital Output, Bit 11
CMOS Digital Output, Bit 10
CMOS Digital Output, Bit 9
CMOS Digital Output, Bit 8
CMOS Digital Output, Bit 7
CMOS Digital Output, Bit 6
CMOS Digital Output, Bit 5
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