28500-DSH-002-C Datasheet, PDF (34/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Introduction
divided as 32 bits (4 bytes) for the transmit direction and 16 bits (3 bytes) for the receive direction. SIU controls
the data access to the Rx and Tx Serial Line Processors. Given that CX28500 supports two types of serial
ports, one is the conventional interface, the other TSBUS interface—SIU needs to operate depending on serial
port type (for detailed descriptor information, see Chapter 5.0).
• Transmit Serial Line Processor (TSLP): This block provides the interface between the DMA and SIU. The data
provided by DMA is processed by TSLP according to the channel type (transparent/HDLC, etc.) before it is
transmitted to the line.
• Receive Serial Line Processor (RSLP): This block provides the interface between the SIU and DMA. The data
provided by SIU is processed by RSLP according to the channel type (transparent/HDLC, etc.) before it is
transmitted to the line.
• RxDMA and TxDMA: This block provides the interface between the Host Memory (PCI) and the Transmit and
Receive Serial Line Processors (TSLP and RSLP). The DMA contains the main storage of data—a dual port
RAM of 32 KB per each direction, receive and transmit. This space acts as a holding buffer for incoming (Rx)
and outgoing (Tx) data.
• JTAG: This is a special test port used for serial boundary scan on a PCB, as well as access to internal scan
paths and embedded memory for test purposes.
1.10
Receive Data Path
At the SIU level, all line signals are synchronized with the system PCI clock, which runs either at 33 MHz or 66
MHz. The received data serial stream is stored in SIU local buffers.
Each cycle, the SIU transfers a byte received from one of the 32 serial ports to the Receive Serial Line Processor
(RSLP). The order in which ports get serviced by the SIU depends on their priorities. A lower numbered port has a
higher priority than a higher numbered port, hence lower number ports are serviced before higher number ports.
For each serial port that was served, SIU translates the time slot into a channel number by using the internal map,
and provides specific parameters for RSLP to further process the incoming data.
The RSLP is a three–stage pipeline processor that performs the functions of an HDLC processor (formatting data),
as well as data concatenation (i.e., to merge bytes in double words) required by RxDMA. The RSLP processed
data is transferred to RxDMA together with a related status, which indicates the status of data.
The RSLP received data is stored in the internal memory before it is transferred to the Host. The internal memory
can be configured on a per-channel basis in programmable units called the channel’s internal buffer space or
channel’s FIFO. The user must configure the channel FIFO in quad dwords granularity by programming the start
and end address of each FIFO (see Table 6-24, RDMA Buffer Allocation Register, bit fields RDMA_ENDAD and
RDMA_STARTAD). When the threshold is crossed, a request to the RxDMA to serve that specific channel is
generated. If either an HDLC complete message (defined by an opening and closing flag) or an EOM message
resides in the channel FIFO, then a request will be generated towards RxDMA to serve the channel regardless of
the threshold value. The request is queued in the RxDMA Service Request Queue, which contains all the channels
pending service requests. The request is serviced when it reaches the top of the RxDMA Service Requests Queue.
If the channel request gets to the top of the RxDMA Service Request Queue, then the RxDMA will transfer the
content of the channel FIFO to the Host memory. After each transaction is completed, the channel is queued at the
end of RxDMA Service Request Queue until all channel data content is transferred to the Host memory.
1.11
Transmit Data Path
For transmit direction, the user allocates the buffer space in quad dwords granularity for each channel by
programming the start and end addresses of each channel FIFO (see Table 6-32, TDMA Buffer Allocation
Register, bit fields TDMA_ENDAD and TDMA_STARTAD). Transmission begins on a request generated by the
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