28500-DSH-002-C Datasheet, PDF (167/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Electrical and Mechanical Specification
Table 10-4. PCI Interface DC Specifications (2 of 2)
Symbol
Parameter
Condition
Min
Max
Units
C_idsel
IDSEL Pin Capacitance⁽³⁾
—
—
8
pF
L_pin
Pin Inductance
—
—
20
nH
FOOTNOTE:
(1) _{Input leakage currents include hi-Z output leakage for all bidirectional buffers with three-state outputs.}
(2) _{Signals without pullup resistors must have 3 mA low output current. Signals requiring pullup must have 6 mA; the latter include}
FRAME*, TRDY*, IRDY*, DEVSEL*, STOP*, SERR*, and PERR*.
(3) _{Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].}
Table 10-5. PCI Clock (PCLK) Waveform Parameters, 3.3 V Clock
Symbol
Parameter
Min
33 MHz
Max
33 MHz
Min
66 MHz
Max
66 MHz
Units
T_cyc
T_high
T_low
—
Clock Cycle Time⁽¹⁾
Clock High Time
Clock Low Time
Clock Slew Rate⁽²⁾
30
Infinite
15
30
ns
11
—
6
—
ns
11
—
6
—
ns
1
4
1.5
4
V/ns
V_ptp
Peak-to-Peak Voltage
0.4 VDD_io
—
0.4 VDD_io
—
V
FOOTNOTE:
(1) _{CX28500 works with any clock frequency between DC and 66 MHz, nominally. The clock frequency may be changed at any time during}
operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times are not violated. The clock
may only be stopped in a low state.
(2) _{Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-}
peak portion of the clock waveform.
Figure 10-1. PCI Clock (PCLK) Waveform, 3.3 V Clock
0.5 V_cc
0.4 V_cc
0.3 V_cc
0.6 VDD_io
T_high
T_cyc
0.2 VDD_io
T_low
V_ptp
(min)
500052_059
28500-DSH-002-C
Mindspeed Technologies^®
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