28500-DSH-002-C Datasheet, PDF (138/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Functional Description
a. While port is not alive (this is equivalent with the correspondent bit not set) wait 8–16 serial line clocks.
b. If port is not alive, poll until port is alive.
c. Otherwise go to the next step.
NOTE:
If the port is not alive in 16 line clocks then there are no serial clocks applied specific port.
8. Initialize the Service Request Pointer (SRP) and Service Request Length (SRL) registers by performing a
direct write to the CX28500’s Service Request Pointer and Service Request Length register and update the
value with the address all the SRP table and its length in shared memory.
9. Perform a CONFIG_WR Service Request and wait for the SACK which copies the content of the register in
shared memory in CX28500 internal register. The Host can performe one CONFIG_WR Service request given
that all the registers have been initialized in the shared memory prior to the CONFIG_WR Service Request or
can perform CONFIG_WR Service Request for each register individually. A detail typical configuration write
request procedure is [13.1]. Allocate the Service Request Table in the shared memory.
NOTE:
1. This allocation can be done in the very beginning (see step 5 or in the configuration
write request procedure) [13.2]. Initialize the content of the Service Request Table.
[13.3]. Initialize the Service Request Pointer (SRP) with the address of Service
Request Table by performing a direct write to the Service Request Pointer register.
[13.3] Start the execution by writing the table length into to the Service Request
Length register by performing a direct write. [13.4]. If other Service Request Table is
required, the Host must poll the Service Request Length register by performing a
direct read and check the SRQ_LEN field. If this field is not 0, then CX28500 did not
complete the execution of the last Service Request Table. The number written in the
SRQ_LEN indicates how many Configuration Write Commands (i.e., table entries) are
pending for execution. While processing these commands, CX28500 generates SACK
interrupt for each command in which the SACKIEN bit was set. When SRQ_LEN
becomes 0, the Host can start from [13.1], whereas prior to a new execution either
frees the memory which was allocated for the prior Service Request Table or uses the
same memory as a pool memory. The registers which are initialized through Service
Request Mechanism are as follows:
2. Global Configuration [1] (one per chip)
3. RSLP Channel Configuration [1024] (for each channel to be activated)
4. RDMA Buffer Allocation [1024] (for each channel to be activated)
5. RDMA Configuration [1024] (for each channel to be activated)
6. RSIU Time slot configuration [4096] (for each time slot to be used)
7. RSIU Time slot Pointer [32] (for each port to be activated)
8. RSIU Port Configuration [32] (for each port which should operate, this command
activates the port)
9. RSLP Max. Message Length [3] (three registers)
10. Receive Base Address Head Pointer [1] (one per chip)
11. Transmit Base Address Head Pointer [1] (one per chip)
12. EBUS configuration [1] (one per chip)
13. TSLP Channel Configuration [1024] (for each channel to be activated)
14. TDMA Buffer Allocation [1024] (for each channel to be activated)
15. TDMA Configuration [1024] (for each channel to be activated)
16. TSIU Time slot Configuration [4096] (for each time slot to be used)
17. TSIU Time slot Pointer [32] (for each port to be activated)
18. TSIU Port Configuration [32](for each port which should operate, this command
activates the port)
28500-DSH-002-C
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