28500-DSH-002-C Datasheet, PDF (106/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Memory Organization
6.5
EBUS Configuration Register
The EBUS Configuration Descriptor, defined in Table 6-21, specifies the configuration parameters for EBUS
transactions. The Host must configure this register before any attempt to access the EBUS.
Table 6-21. EBUS Configuration Register
Bit
Field Name Value
Description
31:14
13
RSVD
ECLKDIV⁽¹⁾
0
Reserved.
0
EBUS clock (ECLK) has the same frequency as the PCI clock (PCLK).
1
EBUS clock (ECLK) has half the frequency of the PCI clock (PCLK).
12
MPUSEL
0
Expansion Bus Microprocessor Selection–Motorola-style. Expansion bus supports the Motorola-style
microprocessor interface and uses Motorola signals: Bus Request (BR*), Bus Grant (BG*), Address
Strobe (AS*), Read/Write (R/WR*), and Data Strobe (DS*).
1
Expansion Bus Microprocessor Selection–Intel-style. Expansion bus supports the Intel-style
microprocessor interface and uses Intel signals: Hold Request (HOLD), Hold Acknowledge (HLDA),
Address Latch Enable (ALE*), Write Strobe (WR*), and Read Strobe (RD*).
11
ECKEN
0
Expansion Bus Clock Disabled. ECLK output is three-stated.
1
Expansion Bus Clock Enabled. CX28500 re-drives and inverts PCLK input onto ECLK output pin.
10:8
ALAPSE[2:0]
— Expansion Bus Address Duration. CX28500 extends the duration of valid address bits during an EBUS
address phase to ALAPSE+1 number of ECLK periods. The control lines ALE* (Intel) or AS* (Motorola)
indicate that the address bits have had the desired setup time.
7:4
BLAPSE[3:0]
— Expansion Bus Access Interval. CX28500 waits BLAPSE number of ECLK periods immediately after
relinquishing the bus. This wait ensures that all the bus grant signals driven by the bus arbiter have
sufficient time to be deasserted as a result of bus request signals being deasserted by CX28500.
3:0
ELAPSE[3:0]
— Expansion Bus Data Duration. CX28500 extends the duration of valid data bits during an EBUS data
phase to ELAPSE+1 number of ECLK periods. The control lines RD* and WR* (Intel) or DS* and R/
WR* (Motorola) indicate the data bits have had the desired setup time.
FOOTNOTE:
(1) _{After reset, the value of EBUS Configuration register is 0, except ECLKDIV bit field, which is 1. The user can change the clock division at}
any time but the EBUS clock must be first reset (disabled), i.e., reset ECKEN bit, and after that a new value of ECLKDIV must be written
with ECKEN set.
6.6
Receive Path Registers
Receive path registers contain the information necessary to configure the receive direction. This configuration
includes registers that are related to the DMA block, Host interface, registers that control the RSLP line processor,
and RSIU.
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