28500-DSH-002-C Datasheet, PDF (202/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-
Back Transactions
In Figure B-6, CX28500 operates at 64-bit address-data and performs a burst read of 4 dwords followed by a burst
write of 6 dwords. The fast back-to-back is disabled. It can be observed that the first cycle requires 3 PCLK cycles
and the second cycle requires 6 PCLK cycles.
Figure B-6. PCI Burst Read Followed by Burst Write
CLK
FRAME#
REQ64#
AD[31:0]
AD[63:32]
C/BE#[3:0]
C/BE#[7:4]
PAR
PAR64
IRDY#
TRDY#
DEVSEL#
ACK64#
Address
Bus Cmd
Data1
Data2
BE1
BE2
Data3
Data4
BE3
BE4
Address
Bus Cmd
Data1
Data2
BE1
BE2
Data3
Data4
BE3
BE4
Data5
Data6
BE5
BE6
GENERAL NOTE:
1. BEx means Byte Enable, where x is a numerical value between 1 and 8. For example, BE1 means byte one is enabled.
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28500-DSH-002-C
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