28500-DSH-002-C Datasheet, PDF (177/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Electrical and Mechanical Specification
Figure 10-12. Transmit and Receive T1 Mode
RCLK
RSYNC-RISE(a)
RDAT A-RISE(a)
RSYNC-RISE(b)
RDAT -FALL(b)
RSYNC-FALL (c)
RDATA-R ISE(c)
RSYNC-FAL L(d)
RDAT -FALL(d)
6
7 F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
6
7
F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
TCLK
TSYNC-RISE(a)
TDAT-R ISE(a)
TSYNC-RISE(b)
TDATA -FALL(b)
6
7
F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
TSYNC-FAL L(c)
TDAT-R ISE(c)
6
7 F-bit 0
1
2
3
4
5
6
7
0
TSYNC-FAL L(d)
TDATA -FALL(d)
6
7 F-bit 0
1
2
3
4
5
6
7
0
GENERAL NOTE:
1. T1 Mode employs 24 time slots (0–23) with 8 bits per time slot (0–7) and 1 Frame-bit every 193 clock periods.
One frame of 193 bits occurs every 125 µs (1.544 MHz).
2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
3. CX28500 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock
edge independently of any other signal sampling configuration.
4. Relationships between the various configurations of active edges for the synchronization signal and the data
signal are shown using a common clock signal for receive and transmit operations. Note the relationship
between the frame bit (within RDAT, TDAT) and the frame synchronization signal (e.g., RSYNC, TSYNC).
5. All received signals (e.g., RSYNC, RDAT, TSYNC) are “sampled” in on the specified clock edge (e.g., RCLK,
TCLK). All transmit data signals (TDAT) are latched on the specified clock edge.
6. In configuration (a), synchronization and data signals are sampled/latched on a rising clock edge.
7. In configuration (b), synchronization signal is sampled on a rising clock edge and the data signal is
sampled/latched on a falling clock edge.
8. In configuration (c), synchronization signal is sampled on a falling clock edge and the data signal is
sampled/latched on a rising clock edge.
9. In configuration (d), synchronization and data signals are sampled/latched on a falling clock edge.
500052_072
28500-DSH-002-C
Mindspeed Technologies^®
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