28529-DSH-001-K Datasheet, PDF (33/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Functional Description
Figure 1-7. M28529 Logic Diagram (UTOPIA-to-Serial)
Reset I
8kHzIn Clock I
Receive Clock I
Receive Data I
Receive Data Marker I
Reset*
8kHzin*
SPRxClk[0]
SPRxData[0]
SPRxSync[0]
Reset
One Second
Interface
Line Interface
Port 0
OneSecIO
SPTxClk[0]
SPTxData[0]
SPTxSync[0]
I/O One Second Input/Output
I Transmit Clock
O Transmit Data
I/O Transmit Data Marker
Receive Clock I
Receive Data I
Receive Data Marker I
PHY Interface Select I
Sync/Async Mode Select I
Microprocessor Clock I
Chip Select I
Address Strobe, Write Control I
Write/Read Read Control I
Address Bus I
Test Reset I
Test Clock I
Test Mode Select I
Test Data Input I
Test Enable I
Test Mode I
ATM Transmit Clock I
ATM Transmit Enable I
ATM Transmit Address Bus I
ATM Receive Clock I
ATM Receive Enable I
ATM Receive Address Bus I
IMA System Clock I
IMA Reference Clock I
Memory Data Bus I/O
External Memory Select I
SPRxClk[31]
SPRxData[31]
SPRxSync[31]
PhyIntFcSel⁽¹⁾
MSyncMode
MicroClk
MCS^*
MAS*, MWr
MW/R, MRd^*
MicroAddr[11:0]
TRST^*
TCK
TMS
TDI
TestEnable
TestMode
atmUTxCLK
atmUTxENB[1:0]^*
atmUTxAddr[4:0]
Line Interface
Port 31
Microprocessor
Interface
JTAG Interface
SPTxClk[31]
SPTxData[31]
SPTxSync[31]
StatOut [1:0]
MicroInt^*
MRdy
MicroData[7:0]
TDO
ATMUTOPIATransmit ^{atmUTxClAv[1:0]}
Interface
atmUTxSOC
atmUTxPrty
atmUTxData[15:0]
atmURxCLK
atmURxENB[1:0]^*
atmURxAddr[4:0]
ATMUTOPIA Receive ^{atmURxClAv[1:0]}
Interface
atmURxSOC
atmURxPrty
atmURxData[15:0]
IMA_SysClk
IMA_RefClk
MemData[15:0]
ExtMemSel
IMA Clocks
TxTRL[1:0]
External Memory
Interface
MemAddr[19:0]
MemCtrl_CE^*
MemCtrl_OE^*
MemCtrl_WE^*
MemCtrl_Clk
MemCtrl_ADSC*
(1)_{Pulled High}
I Transmit Clock
O Transmit Data
I/O Transmit Data Marker
O Status Output
O Summary Interrupt
O Ready
I/O Microprocessor Data Bus
O Test Data Output
O ATM Transmit Cell Available
I ATM Transmit Start Of Cell
I ATM Transmit Parity
I ATM Transmit Data Bus
O ATM Receive Cell Available
O ATM Receive Start Of Cell
O ATM Receive Parity
O ATM Receive Data Bus
O Transmit Reference Clock
O Memory Address Bus
O Chip Enable
O Output Enable
O Write Enable
O SRAM Clock
O Address Enable
28529-DSH-001-K
Mindspeed Technologies^®
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