28529-DSH-001-K Datasheet, PDF (214/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Registers
2.4.22
0x816—IMA_DSL_CLOCK_GEN_ADDR (IMA DSL Clock Generator Control)
This register is used in conjunction with 0x817 to configure the operation of the DSL Clock Generator in the IMA
core. Register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected
using register 0x816 and the configuration for that element is programmed using register 0x817.
The overall operation of the clock generators are governed by the following equations:
• Prescaler Factor = Prescaler Numerator / (Prescaler Terminal Count + 1)
• Intermediate Frequency = Reference Clock Frequency * Prescaler Factor
• Reference Denominator = 257 + Reference Clock Divisor
• 8 kHz = Intermediate Frequency / (Reference Denominator)
Link Payload Rate = 8 kbps * (Multiplier Factor) * (Rate Multiplier)
A further constraint is:
• (Maximum Link Payload Rate) / (Rate Multiplier) ≤ Intermediate Frequency ≤ IMA_SysClk/16
In a typical G.shdsl application, Intermediate Frequency is set to 2.56 MHz, Rate Multiplier = 1, and the Reference
Denominator is set to 320. Other settings are possible as long as the above equations and constraints are met.
Bit
Default
Name
7–5
0
Control Type
4–0
—
—
4-2
—
—
1-0
—
Sub Type
4–0
0x0
Group Number
4–0
0x00 Port Number
Description
0 = Basic Setup
1 = Pre-scaler and Reference Divisor Setup
2 = Tx IMA Group Factor LSBs
3 = Tx IMA Group Factor MSB
4 = Rx IMA Group Factor LSBs
5 = Rx IMA Group Factor MSB
6 = Rx Timing Synthesizer Factor LSBs
7 = Rx Timing Synthesizer Factor MSB
For Control Type = 0
Reserved. Set to 0.
For Control Type = 1
Reserved. Set to 0.
0 = Pre-scaler Terminal Count
1 = Pre-scalar Numerator
2 = Reference Divisor
3 = Reserved
For Control Type = 2, 3, 4, 5
M28525: 0–0xF: IMA Group 1–16
M28529: 0–0x1F: IMA Group 1–32
For Control Type = 6, 7
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
28529-DSH-001-K
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