28529-DSH-001-K Datasheet, PDF (181/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Registers
2.2.28
0x1F—RXMSK4 (Receive Cell Mask Control Register 4)
The RXMSK4 register contains the fourth byte of the Receive Cell Mask. (See 0x1D—RXMSK1.)
Bit
Default
Name
7
1
RxMsk4[7]
6
1
RxMsk4[6]
5
1
RxMsk4[5]
4
1
RxMsk4[4]
3
1
RxMsk4[3]
2
1
RxMsk4[2]
1
1
RxMsk4[1]
0
1
RxMsk4[0]
Description
These bits hold the Receive Header Mask for Octet 4 of the incoming cell.
2.2.29
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1)
The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the cell
receiver. Idle cells are discarded from the received stream if register CVAL (0x0C) bit 6 is set to 1. This header
consists of 32 bits divided among four registers.
Bit
Default
Name
7
0
RxIdl1[7]
6
0
RxIdl1[6]
5
0
RxIdl1[5]
4
0
RxIdl1[4]
3
0
RxIdl1[3]
2
0
RxIdl1[2]
1
0
RxIdl1[1]
0
0
RxIdl1[0]
Description
These bits hold the Receive Idle cell header for Octet 1 of the incoming cell.
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