28529-DSH-001-K Datasheet, PDF (269/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Product Specification
Table 3-10. Microprocessor Timing Parameters - Synchronous Write
Label
Description
Minimum
t_per
Microprocessor clock period
40
t_duty Microprocessor Clock Period Duty Cycle
40
t_s
Setup to the rising edge of MicroClk
5
t_h
Hold from the rising edge of MicroClk
2
t_enzl Enable from the rising edge of MicroClk
2
Footnote:
(1) Timing relative to a 50pF load
Maximum
60
—
—
15
Units
ns
%
ns
ns
ns
3.4.3
PHY-side Interface Timing (Serial Mode)
The PHY-side interface on the MaxIMA supports three different modes of operation, serial, interleaved and
UTOPIA. Figure 3-8 through 3-13 show the timing diagrams for T1/E1/DSL mode. Table 3-11 and Table 3-12 show
the PHY-side timing requirements for T1/E1/DSL mode.
Figure 3-8. PHY-side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 0, TxDatShft = 0)
S P T x C lk
S P T xS ync
(In p ut)
SPTxSync
(O u tp u t)
S P T xD a ta
tpw h
tper
tpw l
ts
t_h
t_s
th
t pd
t pd
t _pd
Figure 3-9. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 1, TxDatShft = 0)
S P T x C lk
S P T xS ync
(In p u t)
S P T xS ync
(O u tp u t)
S P T xD a ta
tpw h
tper
tpw l
ts
t_h
ts
th
t pd
t pd
t _pd
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