28529-DSH-001-K Datasheet, PDF (1/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

M28525/9 Data Sheet
Inverse Multiplexing for ATM (IMA) Family
The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32 ports.
All devices include a Transmission Convergence block to perform cell delineation, 512 K internal RAM to meet ATM
forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer interface.
Source code for all required software functions is available from Mindspeed. The M28529 supports 32 IMA groups
with 1-32 links per group.
The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams
without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead.
The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In
addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external
RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001
Distinguishing Features
• Complete IMA solution in a single package
• 16 port, M28525
• 32 port, M28529
• Field tested software available
• Up to 32 IMA groups with 1-32 links/group
• Supports 50 ms (beyond the IMA standard requirements for 25 ms)
differential delay with 512K Internal memory
• Memory expandable to 2 M bytes via external bus
• UTOPIA level 2 interfaces
• Glueless serial and interleaved highway interfaces to Mindspeed
Framers
• Octet or Bit level cell delineation
• Variable link data rates (64K–8.192 Mb/s)
Functional Block Diagram
M 28529
E xte rn a l M e m o ry
In te rfa c e
In te rn a l
512Kx8
SR AM
0
1
e x tm e m s e l p in
Di if f e r e n t ia l D e la y
m e m o r y in t e r f a c e
R x B lo c k a n d
P assthrough
IM A
E n g in e
T x B lo c k a n d
P assthrough
IM A
B lo c k
T C B lo c k
C e ll
proc es s or
C e ll
proc es s or
L in e in t e r f a c e
0
L in e in t e r f a c e
1
TC
C o un te r s
C e ll
proc es s or
C e ll
proc es s or
L in e in t e r f a c e 3 0
L in e in t e r f a c e 3 1
T C S tatus
R e g is te r s
T C C o n tr ol
R e g is te r s
O n eSec
IM A c lo c ks
JT AG
M ic ro
In te rf a c e
M icro
C lo c ks
* N o t e : T h e M 2 8 5 2 5 o n ly s u p p o rt s 1 6 T C P o rt s
28529-DSH-001-K
Mindspeed Technologies^®
Mindspeed Proprietary and Confidential
September 2007