LTC3447_15 Datasheet, PDF (8/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
U
OPERATIO
the user should calculate the power dissipation when
the LTC3447 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
Low Supply Operation
The LTC3447 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current
is reduced at this low voltage. Figure 4 shows the reduc-
tion in the maximum output current as a function of input
voltage for various output voltages.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles >40%; however, the LTC3447 uses a
patent-pending scheme that counteracts this compensat-
ing ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
DAC
The I²C interface is used to control the internal voltage
DAC for the buck regulator. The output voltage range is
0.69V to 2.05V in 21.6mV steps. The default DAC setting
is 100000 which equates to a 1.38V output voltage. Output
voltage transitions begin once the I²C interface receives
the STOP command.
Slew Rate
The LTC3447 has a slew rate of approximately 11mV/µs.
The slew rate is controlled by the RC time constant of a
low pass filter at the voltage DAC output. Figure 5 shows
a typical transition from min to max DAC settings.
1200
T_A = 25°C
1100
DAC = MIN
1000
900
DAC = MAX
800
700
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
3447 F04
Figure 4. Maximum Load Current vs Supply Voltage
500mV/DIV
BURST MODE OPERATION
V_IN = 3.6V
V_OUT
INDUCTOR CURRENT
200mA/DIV
5V/DIV
PGOOD
100µs/DIV
Figure 5.Transition from DAC = MIN to DAC = MAX
SDA
SCL
1-7
S
START
ADDRESS
COMMAND
8
8
9
1-7
8
9
1-7
8
R/W
ACK
DATA
ACK
DATA
Figure 6. Typical I²C Write Protocol
9
P
ACK
ST0P
COMMAND
3447 TD02
3447f