LTC3447_15 Datasheet, PDF (10/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
U
OPERATIO
The START and STOP Commands
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission
with a START command by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP command
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge signal (LOW
active) is generated by the slave lets the master know that
the latest byte of information was received. The acknowl-
edge-related clock pulse is generated by the master. The
transmitter master releases the SDA line (HIGH) during
the acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains stable LOW during the HIGH period of
this clock pulse.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must
be left HIGH by the slave. The master can then generate
a STOP command to abort the transfer.
If a slave receiver does acknowledge the slave address but,
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP command. The
data line is also left high by the slave and master after a
slave has transmitted a byte of data to the master in a read
operation, but this is a not acknowledge that indicates that
the data transfer is successful.
Commands Supported
The LTC3447 supports only write byte commands to a
single register. During ACK bit periods, the LTC3447 will
pull the data line low to acknowledge the master device.
See Figure 7.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into
the part, data from a write command is only stored after
a valid STOP command has been performed.
WRITE BYTE PROTOCOL
1
7
1
1
8
1
1
START
1100110
SLAVE
ADDRESS
0
ACK
WRITE
XXXXXXXX
DATA
ACK
STOP
I²C REGISTER DEFINITION
MSB
7
6
5
4
3
2
1
0
LSB
DISABLE
ENABLE
BUCK
BUCK
BUCK
BUCK
BUCK
BUCK
BURST
PGOOD
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
(DEFAULT = 0) BLANKING (DEFAULT = 1) (DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0) (DEFAULT = 0)
(DEFAULT = 0)
3447 F07
Figure 7. LTC3447’s Write I²C Protocol
3447f
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