LTC3447_15 Datasheet, PDF (14/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
APPLICATIO S I FOR ATIO
junction temperature of the part. The temperature rise
is given by:
T_R = θ_JA • P_D
where P_D is the power dissipated by the regulator and
θ_JA is the thermal resistance from the junction of the die
to the temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3447 when using an input
voltage of 3.6V, an ambient temperature of 70°C, and a
buck load current of 500mA. From the typical performance
graph of switch resistance, the R_DS(ON) of the P-channel
switch at 70°C is approximately 0.45Ω. Therefore, power
dissipated by the part is:
P_D = I_LOAD2 • R_DS(ON) = 112.5mW
For the DFN-10 package, the θ_JA is 43°C/W. Thus, the
junction temperature of the regulator is:
T_J = 70°C + (0.1125)(43) = 74.8°C
which is well below the maximum junction temperature of
150°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(R_DS(ON)).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3447. These items are also illustrated graphically
in Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the
SW trace, and the V_IN trace should be kept short, direct
and wide.
2. Does the V_OUT pin connect directly to the output voltage
reference? Ensure that there is no load current running
from the output voltage and the V_OUT sense pin.
3. Does the FB pin connect directly to the feedback voltage
reference? Ensure that there is no load current running
from the feedback reference voltage and the FB pin.
4. Does the (+) plate of C_IN connect to V_IN as closely as
14
possible? This capacitor provides the AC current to the
internal power MOSFETs.
5. Keep the switching node, SW, away from the sensitive
V_OUT and FB nodes.
6. Keep the (–) plates of C_IN and C_OUT as close as pos-
sible.
R2
GND PLANE
R1
V_OUT
GND
FB
PGOOD
V_IN
V_IN
C_IN
SDA
V_CCD
SCL
RUN
SW
C2
L1
GND PLANE
C_OUT
VIA
TO
V_OUT
3447 F09
Figure 9. LTC3447 Suggested Layout
V_OUT
R1
GND
R2
FB
SDA
V_CCD
C2
SCL
PGOOD
RUN
V_IN
SW
C_IN
C_OUT
L1
V_IN
V_OUT
3447 F11
Figure 10. LTC3447 Layout Diagram
3447f