LTC3447_15 Datasheet, PDF (15/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
APPLICATIO S I FOR ATIO
Design Example
As a design example, assume the LTC3447 is used in a
single lithium-ion battery-powered cellular phone applica-
tion. The V_IN will be operating from a maximum of 4.2V
down to about 2.7V. The normal load current requirement
is a maximum of 500mA at 1.4V, but most of the time it will
be in standby mode, requiring only 200µA at 1V. Efficiency
at both low and high load currents is important.
To ensure that the ripple currents and voltages do not
exceed desired expectations over the DAC output range,
calculations with maximum V_IN and minimum V_OUT should
be used. Note that either increasing the output voltage or
decreasing V_IN will result in a decrease of ripple current
and voltage. Choosing a maximum ripple current, ΔI_L, of
280mA, Equation 1 can be used to determine the size of
the inductor that should be used.
L
=
1
(1MHz)(280mA)
•
1.4V^{⎛⎝⎜}1–
1.4V
4.2V
⎞⎠⎟
=
3.3µH
A 3.3µH inductor works well for this application. For best
efficiency choose a 640mA or greater inductor with less
than 0.2Ω series resistance.
C_IN will require an RMS current of at least 0.25A, approxi-
mately I_LOAD(MAX)/2, overtemperature (see Equation 2). For
C_OUT, selecting a 4.7µF capacitor with an ESR of 0.25Ω
yields the following ripple voltage using Equation 3.
∆V_OUT
=
0.280A^{⎛⎝⎜} 0.25Ω
+
1
⎞
8(1MHz)(4.7µF)⎠⎟
=
70mV + 7.4mV = 77.4mV
Note that the majority of the ripple voltage is generated
by the capacitor’s ESR. Most ceramic capacitors will have
a typical ESR of 10mΩ or less. Selecting capacitors with
low ESRs will significantly reduce the ripple voltage.
Efficiency can be improved by taking advantage of the
LT3447’s Burst Mode operation. When entering the standby
mode, ensure that the burst disable bit is set to 0 when
the output voltage DAC is updated. Likewise, when enter-
ing a heavy current load mode, ensure the burst disable
bit is set to 1 when the output voltage DAC is updated.
Figure 11 shows the advantage of utilizing the Burst Mode
function.
100
STBY _DAC(MAX)
90
DAC(MAX)
80
70
NORMAL
60
DAC(MIN)
50
40
30
20
10
DAC(MIN)
0
0.1
1
BURST
PSK
10
100
1000
LOAD CURRENT (mA)
3447 F11
Figure 11. Efficiency vs Load Current ( V_IN = 4.2V)
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.675 ±0.05
R = 0.115
TYP
6
0.38 ± 0.10
10
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10 1.65 ± 0.10
(4 SIDES) (2 SIDES)
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
PIN 1
PACKAGE TOP MARK
OUTLINE (SEE NOTE 6)
0.200 REF
0.75 ±0.05
0.00 – 0.05
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3447f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
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