LTC3447_15 Datasheet, PDF (13/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
APPLICATIO S I FOR ATIO
loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 8.
1
0.1
0.01
DAC = MAX
DAC = MIN
0.001
0.1
1
10
100
LOAD CURRENT (mA)
1000
3447 F08
Figure 8. Power Loss vs Load Current
The V_IN quiescent current is due to two components: the
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V_IN to ground. The resulting dQ/dt is the current out
of V_IN that is typically larger than the DC bias current. In
continuous mode, I_GATECHG = f(QT + QB) where QT and
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V_IN and thus their effects will be more
pronounced at higher supply voltages.
I²R losses are calculated from the resistances of the internal
switches, R_SW, and external inductor R_L. In continuous
mode, the average output current flowing through inductor
L is “chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into the
SW pin is a function of both top and bottom MOSFET
R_DS(ON) and the duty cycle (DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses including C_IN and C_OUT ESR dissipative losses
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (ΔI_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ΔI_LOAD also begins to charge or dis-
charge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C_OUT, causing a rapid drop in V_OUT. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately (25
• C_LOAD). Thus, a 10µF capacitor charging to 3.3V would
require a 250µs rise time, limiting the charging current
to about 130mA.
Thermal Considerations
In most applications the LTC3447 does not dissipate much
heat due to its high efficiency. But, in applications where the
LTC3447 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
To avoid the LTC3447 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
3447f
13