LTC3447_15 Datasheet, PDF (2/16 Pages) Linear Technology – I2C Controllable Buck Regulator

LTC3447
ABSOLUTE AXI U RATI GS
(Note 1)
V_IN, V_CCD Voltages ....................................... –0.3V to 6V
RUN, V_OUT, FB Voltages .............................. – 0.3V to V_IN
SW Voltage ................................... –0.3V to (V_IN + 0.3V)
SCL, SDA Voltages................................... – 0.3V to V_CCD
P-Channel Switch Source Current (DC) ...............800mA
N-Channel Switch Sink Current (DC) ...................800mA
Peak SW Sink and Source Current ...........................1.3A
Operating Temperature Range (Note 2) ...–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
UW U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V_OUT 1
GND 2
FB 3
PGOOD 4
V_IN 5
10 SDA
9 V_CCD
11
8 SCL
7 RUN
6 SW
DD PACKAGE
10-LEAD (3mm x 3mm)PLASTIC DFN
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
T_JMAX = 125°C, θ_JA = 43°C/W, θ_JC = 2.96°C/W
ORDER PART
NUMBER
LTC3447EDD
DD PART
MARKING
LBKB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
RUN
Run Threshold
0.3
1
1.5
PGOOD
Reports Undervoltage
PGOOD = 0.4V
3
R_VOUT
V_OUT(MIN)
V_OUT(MAX)
V_OUT
Feedback Resistance
Regulated Output Voltage
Regulated Output Voltage
Output Voltage Step Size (6-bits)
460
● 0.669 0.69 0.711
● 1.989 2.05 2.112
● 20.3 21.6 22.9
ΔV_OUT
Output Voltage Line Regulation
V_IN = 2.5V to 5.5V (Note 6)
●
0.2
1.2
0.2
1
I_PK
V_LOADREG
V_IN
I_S
f_OSC
R_PFET
R_NFET
I_LSW
FB
Peak Inductor Current
Output Voltage Load Regulation
Input Voltage Range
Input DC Bias Current
Burst Mode Operation
Active Mode
Shutdown
Nominal Oscillator Frequency
R_DS(ON) of P-Channel FET
R_DS(ON) of N-Channel FET
SW Leakage
Optional Start-Up Feedback Voltage
Duty Cycle < 35%, Wafer Level
(Note 4)
I_LOAD = 0A
V_OUT = 90%, I_LOAD = 0A
V_RUN = 0V, V_IN = 5.5V
V_OUT = 100%
V_OUT = 0V
I_SW = 100mA, Wafer Level
I_SW = –100mA, Wafer Level
V_RUN = 0V, V_SW = 0V or 5V, V_IN = 5V
Regulated Feedback Voltage
0.75
1
1.25
0.5
● 2.5
5.5
34
60
280
400
0.1
1
● 0.7
1
1.3
160
0.32
0.22
±0.1
±1
0.6
I_FB
SCL_THR
SCL_HYST
SDA_THR
SDA_HYST
Feedback Input Current
I²C Clock Logic Threshold
I²C Clock Logic Hysteresis
I²C Data Logic Threshold
I²C Data Logic Hysteresis
(Note 5)
(Note 5)
(Note 5)
(Note 5)
2.5
10
V_CCD/2
300
V_CCD/2
300
UNITS
V
mA
kΩ
V
V
mV
%/V
%/V
A
%
V
µA
µA
µA
MHz
kHz
Ω
Ω
µA
V
nA
V
mV
V
mV
3447f
2