LTC3717 Datasheet, PDF (6/20 Pages) Linear Technology – Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination

LTC3717
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
PGOOD (Pin 2): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
V_RNG (Pin 3): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTV_CC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTV_CC.
I_TH (Pin 4): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
SGND (Pin 5): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
I_ON (Pin 6): On-Time Current Input. Tie a resistor from V_IN
to this pin to set the one-shot timer current and thereby set
the switching frequency.
V_FB (Pin 7): Error Amplifier Feedback Input. This pin
connects to V_OUT and divides its voltage to 2/3 • V_FB
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than
1.5V on V_FB. For higher output voltages, attach an external
resistor R2 (1/2 • R1 at V_REF) from V_OUT to V_FB.
V_REF (Pin 8): Positive Input of Internal Error Amplifier.
This pin connects to an external reference and divides its
voltage to 1/3 V_REF through precision internal resisters
before it is applied to the positive input of the error
amplifier. Reference voltage for output voltage, power
good threshold, and short-circuit shutdown threshold. Do
not apply more than 3V on V_REF. If higher voltages are
used, connect an external resistor (R1 ≥ 160k) from
voltage reference to V_REF.
EXTV_CC (Pin 9): External V_CC Input. When EXTV_CC ex-
ceeds 4.7V, an internal switch connects this pin to INTV_CC
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTV_CC. Do not exceed
7V at this pin and ensure that EXTV_CC < V_CC.
V_CC (Pin 10): Bias Input Supply. 4V to 36V operating
range. Decouple this pin to PGND with an RC filter (1Ω,
0.1µF).
INTV_CC (Pin 11): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. De-
couple this pin to power ground with a minimum of 4.7µF
low ESR tantalum or ceramic capacitor.
BG (Pin 12): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTV_CC.
PGND (Pin 13): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of C_VCC and the (–) terminal of C_IN.
SW (Pin 14): Switch Node. The (–) terminal of the boot-
strap capacitor C_B connects here. This pin swings from a
diode voltage drop below ground up to a diode voltage
drop above V_IN.
TG (Pin 15): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTV_CC superim-
posed on the switch node voltage SW.
BOOST (Pin 16): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor C_B connects here. This
pin swings from a diode voltage drop below INTV_CC up to
V_IN + INTV_CC.
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