LTC3717 Datasheet, PDF (16/20 Pages) Linear Technology – Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination

LTC3717
APPLICATIO S I FOR ATIO
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V_IN, V_OUT, GND or to any other DC rail in
your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 7.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTV_CC decoupling capacitor C_VCC closely
to the INTV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to the
BOOST and SW pins.
• Connect the V_CC pin decoupling capacitor C_F closely to
the V_CC and PGND pins.
C_SS
C_{C1 RC}
C_ION
C_FB
LTC3717
1 _{RUN/SS BOOST} 16
2 _PGOOD
TG ¹⁵
3
V_RNG
4 _ITH
C_{C2 5}
SGND
14
SW
13
PGND
BG ¹²
6
I_ON
7 _VFB
8
V_REF
11
INTV_CC
V_CC ¹⁰
9
EXTV_CC
C_B
D_B
C_VCC
C_F
R_F
L
M1
D2
M2
D1
C_IN
C_OUT
+
V_IN
–
–
V_OUT
+
R_ON
BOLD LINES INDICATE HIGH CURRENT PATHS
3717F07
Figure 7. LTC3717 Layout Diagram
16
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