LTC3717 Datasheet, PDF (14/20 Pages) Linear Technology – Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination

LTC3717
APPLICATIO S I FOR ATIO
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. C_IN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I²R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C_OUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to ∆I_LOAD (ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating a feedback error signal used by
the regulator to return V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I_TH pin external components shown in Figure 6
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V_IN = V_REF = 2.5V, V_EXTVCC = 5V, V_OUT =
1.25V ±5%, I_OUT(MAX) = 10A, f = 250kHz. First, calculate
the timing resistor with V_ON = V_OUT:
R_ON
=
1.25V(2.5V – 0.7V)
(0.7V)(250kHz)(10pF)2.5V
=
514kΩ
and choose the inductor for about 40% ripple current at
the maximum V_IN:
14
L
=
1.25V
(250kHz)(0.4)(10A)

^1−
1.25V ^
2.5V 
=
0.63µH
Selecting a standard value of 0.68µH results in a maximum
ripple current of:
∆I_L
=
1.25V
(250kHz)(0.68µH)

^1–
1.25V ^
2.5V 
=
3.7A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R_DS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θ_JA = 40°C/W) yields a nominal sense voltage of:
V_SNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying V_RNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ_110°C = 1.4:
I_LIMIT
≥
143mV
(1.4)(0.010Ω)
+
1 _(3.7A)
2
=
12.1A
and double check the assumed T_J in the MOSFET:
P_BOT
=
2.5V – 1.25V
2.5V
(12.1A)²(1.4)(0.010Ω)
= 1.02W
T_J = 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C_IN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.
sn3717 3717fs