LTC3577_15 Datasheet, PDF (47/54 Pages) Linear Technology – Highly Integrated 6-Channel Portable PMIC

LTC3577/LTC3577-1
OPERATION
Hard Reset Timing
Hard reset provides an ultralow power-down state for
shipping or long-term storage as well as a way to power
down the application in case of a software lock-up. In the
case of software lock-up ON is brought low by the user
applying the pushbutton. If the user holds the pushbutton
for 5 seconds a hard reset event (HRST) will occur placing
the pushbutton circuitry in the PDN1 state. At this point
the bucks, LDOs and LED backlight will all be shut down
and WAKE and PG_DCDC will both go low. Following a 1
second power-down period the pushbutton circuitry will
enter the hard reset state (HR).
Holding ON low through the 1 second power-down period
will not cause a power-up event at end of the 1second period.
The ON must be brought high following the power-down
event and then go low for again for 400ms to establish a
valid power-up event as shown in Figure 24.
BAT
ON (PB)
PBSTAT
WAKE
BUCKS
PWR_ON
PG_DCDC
STATE
5SEC
1SEC
400ms
123
PON
PDN1
HR
PUP
3577 F24
Power-Up Sequencing
Figure 25 shows the actual power-up sequencing of the
LTC3577. Buck1, buck2 and buck3 are all initially disabled
(0V). Once the pushbutton has been applied (ON low) for
400ms, WAKE goes high and buck1 is enabled. Buck1
slews up and enters regulation once enabled. The actual
slew rate is controlled by the soft-start function of buck1
in conjunction with output capacitance and load (see the
“Step-Down Switching Regulator Operation” section for
more information). When buck1 is within about 8% of final
regulation, buck2 is enabled and slews up into regulation.
Finally when buck2 is within about 8% of final regulation,
buck3 is enabled and slews up into regulation. 230ms
after buck3 is within 8% of final regulation the PG_DCDC
output will go high impedance (not shown in Figure 25).
The regulators in Figure 25 are slewing up with nominal
output capacitors and no load. Adding a load or increasing
output capacitance on any of the outputs will reduce the
slew rate and lengthen the time it takes the regulator to get
into regulation. Reducing the slew rate also pushes out the
time until the next regulator is enabled proportionally.
1
WAKE
0
BUCK1
2V/DIV
0V
BUCK2
1V/DIV
0V
BUCK3
1V/DIV
0V
50μs/DIV
3577 F23
Figure 24. Hard Reset Timing
Figure 25. Power-Up Sequencing
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