LTC3577_15 Datasheet, PDF (40/54 Pages) Linear Technology – Highly Integrated 6-Channel Portable PMIC

LTC3577/LTC3577-1
OPERATION
I²C Slave Address
The LTC3577 responds to a 7-bit address which has been
factory programmed to b’0001001[R/W]’. The LSB of
the address byte, known as the read/write bit, should be
0 when writing data to the LTC3577 and 1 when reading
data from it. Considering the address an eight bit word,
then the write address is 0x12 and the read address is
0x13. The LTC3577 will acknowledge both its read and
write address.
I²C Sub-Addressed Writing
The LTC3577 has four command registers for control
input. They are accessed by the I²C port via a sub-
addressed writing system.
Each write cycle of the LTC3577 consists of exactly three
bytes. The first byte is always the LTC3577’s write address.
The second byte represents the LTC3577’s sub-address.
The sub address is a pointer which directs the subsequent
data byte within the LTC3577. The third byte consists of
the data to be written to the location pointed to by the sub-
address. The LTC3577 contains control registers at only
four sub-address locations: 0x00, 0x01, 0x02 and 0x03.
Writing to sub-addresses outside the four sub-addresses
listed is not recommended as it can cause data in one of
the four listed sub-addresses to be overwritten.
I²C Bus Write Operation
The master initiates communication with the LTC3577
with a START condition and the LTC3577’s write address.
If the address matches that of the LTC3577, the LTC3577
returns an acknowledge. The master should then deliver
the sub-address. Again the LTC3577 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of
its acknowledge by the LTC3577. This procedure must be
repeated for each sub-address that requires new data. After
one or more cycles of [ADDRESS][SUB-ADDRESS][DATA],
the master may terminate the communication with a STOP
condition. Alternatively, a REPEAT-START condition can be
initiated by the master and another chip on the I²C bus can
be addressed. This cycle can continue indefinitely and the
LTC3577 will remember the last input of valid data that it
received. Once all chips on the bus have been addressed
and sent valid data, a global STOP can be sent and the
LTC3577 will update its command latches with the data
that it had received.
I²C Bus Read Operation
The bus master reads the status of the LTC3577 with a
START condition followed by the LTC3577 read address. If
the read address matches that of the LTC3577, the LTC3577
returns an acknowledge. Following the acknowledgement
of its read address the LTC3577 returns one bit of status
information for each of the next 8 clock cycles. A STOP
command is not required for the bus read operation.
I²C Input Data
There are 4 bytes of data that can be written to on the
LTC3577. The bytes are accessed through the sub-
addresses 0x00 to 0x03. At first power application (V_BUS,
WALL or BAT) all bits default to 0. Additionally all bits are
cleared to 0 when DV_CC drops below its undervoltage lock
out or if the pushbutton enters the power-down (PDN1
or PDN2) state.
Table 8. LDO and Buck Control Register
LDO and BUCK
CONTROL REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000000
BIT NAME
FUNCTION
B0 LDO1EN
Enable LDO 1
B1 LDO2EN
Enable LDO 2
B2 BK1BRST
Buck1 Burst Mode Enable
B3 BK2BRST
Buck2 Burst Mode Enable
B4 BK3BRST
Buck2 Burst Mode Enable
B5 SLEWCTL1
B6 SLEWCTL2
Buck SW Slew Rate: 00 = 1ns,
01 = 2ns, 10 = 4ns, 11 = 8ns
B7 N/A
Not Used—No Effect on Operation
Table 8 shows the first byte of data that can be written to
at sub-address 0x00. This byte of data is referred to as
the “LDO and buck control register.”
Bits B0 and B1 enable and disable the LDOs. Writing 1
to B0 or B1 will enable LDO1 or LDO2 respectively, while
writing a 0 will disable the respective LDO.
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