LTC3577_15 Datasheet, PDF (39/54 Pages) Linear Technology – Highly Integrated 6-Channel Portable PMIC

LTC3577/LTC3577-1
OPERATION
I²C Timing Diagram
00
START
SDA
00
ADDRESS
0100
WR
10
DATA BYTE A
A7 A6 A5 A4 A3 A2 A1 A0
DATA BYTE B
B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 0 1 0 ACK
ACK
ACK
STOP
SCL
123456789123456789123456789
SDA
t_LOW
t_{SU, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_r
t_f
t_{HD, DAT}
t_{SU, STA}
t_{HD, STA}
t_SP
REPEATED START
CONDITION
t_BUF
t_{SU, STO}
3577 TD
STOP
CONDITION
START
CONDITION
I²C Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
I²C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3577, the master may transmit a STOP condition which
commands the LTC3577 to act upon its new command set.
A STOP condition is sent by the master by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is
then free for communication with another I²C device.
I²C Byte Format
Each byte sent to or received from the LTC3577 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3577
most significant bit (MSB) first.
I²C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3577 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC3577 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC3577.
An acknowledge (active LOW) generated by the LTC3577
lets the master know that the latest byte of information was
received. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3577 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.
When the LTC3577 is read from, it releases the SDA line so
that the master may acknowledge receipt of the data. Since
the LTC3577 only transmits one byte of data, a master not
acknowledging the data sent by the LTC3577 has no I²C
specific consequence on the operation of the I²C port.
3577fa
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