LTC3577_15 Datasheet, PDF (30/54 Pages) Linear Technology – Highly Integrated 6-Channel Portable PMIC

LTC3577/LTC3577-1
OPERATION
MN1
V1
V2
D2
D1 ^MN2
WALL
OVGATE
LTC3577
V_BUS
C1
R1
OVSENS
3577 F10
Figure 10. Dual Input Overvoltage Protection
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
“Overvoltage Protection” section for an explanation of
this calculation. Table 2 shows some NMOS FETs that are
suitable for overvoltage protection.
Table 2. Recommended Overvoltage FETs
NMOS FET
Si1472DH
BVDSS
30V
R_ON
82mΩ
Si2302ADS
20V
60mΩ
Si2306BDS
30V
65mΩ
Si2316BDS
30V
80mΩ
IRLML2502
20V
35mΩ
PACKAGE
SC70-6
SOT-23
SOT-23
SOT-23
SOT-23
Reverse Input Voltage Protection
The LTC3577 can also be easily protected against the
application of reverse voltage as shown in Figure 10. D1
and R1 are necessary to limit the maximum VGS seen by
MP1 during positive overvoltage events. D1’s breakdown
voltage must be safely below MP1’s BVGS. The circuit
shown in Figure 11 offers forward voltage protection up
to MN1’s BVDSS and reverse voltage protection up to
MP1’s BVDSS.
LOW DROPOUT LINEAR REGULATOR OPERATION
LDO Operation and Voltage Programming
The LTC3577 contains two 150mA adjustable output LDO
regulators. To enable the LDOs write a 1 to the LDO1EN
and/or LDO2EN I²C registers. The LDOs can be disabled
three ways: 1) Write a 0 to the LDO1EN and LDO2EN
registers; 2) Bring DV_CC below the DV_CC undervoltage
threshold; 3) Enter the power-down pushbutton state.
30
USB/WALL
ADAPTER
MP1
MN1
D1
R1
R2
500k
6.2k
V_BUS
C1
LTC3577
OVGATE
OVSENS
3577 F11
D1: 5.6V ZENER
MP1: Si2323DS, BVDSS = 20V
V_BUS POSITIVE PROTECTION UP TO BVDSS OF MN1
V_BUS NEGATIVE PROTECTION UP TO BVDSS OF MP1
Figure 11. Dual Polarity Voltage Protection
LDOxEN ⁰
1
V_INLDOx
MP
LDOx
R1
LDOx_FB
0.8V
GND
R2
LDOx
OUTPUT
C_OUT
3577 F12
Figure 12. LDO Application Circuit
The LDOs are further disabled if V_OUT falls below the V_OUT
UVLO threshold and cannot be enabled until the UVLO
condition is removed.
When disabled all LDO circuitry is powered off leaving only
a few nanoamps of leakage current on the LDO supply.
The LDO outputs are individually pulled to ground through
internal resistors when disabled.
The power good status bits of LDO1 and LDO2 are avail-
able in I²C through the read-back registers PGLDO[1] and
PGLDO[2] for LDO1 and LDO2 respectively. The power
good comparators for both LDOs are sampled when the
I²C port receives the correct I²C read address.
Figure 12 shows the LDO application circuit. The full-
scale output voltage for each LDO is programmed using
a resistor divider from the LDO output (LDO1 or LDO2)
connected to the feedback pins (LDO1_FB or LDO2_FB)
such that:
V_LDOx
=
0.8V
•
⎛
⎝⎜
R1
R2
+
1^{⎞⎠⎟}
3577fa