LTC3577_15 Datasheet, PDF (45/54 Pages) Linear Technology – Highly Integrated 6-Channel Portable PMIC

LTC3577/LTC3577-1
OPERATION
Power-Up via External Power Timing
The timing diagram, Figure 20, shows the LTC3577 power-
ing up through application of the external power (V_BUS or
WALL). For this example the pushbutton circuitry starts
in the POFF or HR state with a battery connected and all
buck disabled. 100ms after WALL or V_BUS application the
WAKE output goes Hi-Z for 5 seconds. The 100ms delay
time allows the applied supply to settle. WAKE going
Hi-Z sequences buck1-3 up in numerical order. WAKE
will stay Hi-Z if the PWR_ON input is driven high before
the 5 seconds PUP period is over. If PWR_ON is low or
goes low after the 5 second period, WAKE will go low and
buck1-3 will be shut down together. PG_DCDC is asserted
once all enabled bucks are within 8% of their regulation
voltage for 230ms.
The LDOs and LED backlight can be enabled and disabled
via I²C any time after entering the PUP1, PUP2 or PON
state. The PWR_ON input can be driven via a μP/μC or one
of the buck outputs through a high impedance (100kΩ
typ) to keep the bucks enabled as described above.
Without a battery present initial power application causes
a power on reset which puts the pushbutton circuitry in
the PDN2 state and subsequently the HR state 1 second
later. In this case the pushbutton must be applied to enter
the PUP1 state after initial power application.
BAT
V_BUS
ON (PB)
PBSTAT
WAKE
BUCK1-3
PG_DCDC
100ms
BUCKS SEQUENCE UP
123
230ms
PWR_ON
STATE POFF/HR
PUP2/PUP1
5SEC
PON
3755 F20
Figure 20. Power-Up via External Power Timing
Power-Up via PWR_ON Timing
The timing diagram, Figure 21, shows the LTC3577
powering up by driving PWR_ON high. For this example
the pushbutton circuitry starts in the POFF or HR state
with a battery connected and all bucks disabled. 50ms
after PWR_ON goes high the WAKE output goes Hi-Z for
5 seconds. WAKE going Hi-Z sequences buck1-3 up in
numerical order. WAKE will stay Hi-Z as long as PWR_ON
is high at the end of the 5 second PUP period. If PWR_ON
is low or goes low after the 5 second period, WAKE will
go low and buck1-3 will be shut down together. PG_DCDC
is asserted once all enabled bucks are within 8% of their
regulation voltage for 230ms.
The LDOs and LED backlight can be enabled and disabled
via I²C any time after entering the PUP1, PUP2 or PON
state.
Powering up via PWR_ON is useful for applications
containing an always on μC. This allows the μC to power
the application up and down for house keeping and other
activities outside the user’s control.
BAT
ON (PB)
PBSTAT
PWR_ON
WAKE
BUCK1-3
PG_DCDC
STATE
5Oms
BUCKS SEQUENCE UP
123
230ms
POFF/HR
PUP2/PUP1
5SEC
PON
3577 F21
Figure 21. Power-Up via PWR_ON Timing
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