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LTC3300-2_15 Datasheet, PDF (36/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer
LTC3300-2
APPLICATIONS INFORMATION
PCB Layout Considerations
The LTC3300-2 is capable of operation with as much as
40V between BOOST+ and V–. Care should be taken on
the PCB layout to maintain physical separation of traces
at different potentials. The pinout of the LTC3300-2 was
chosen to facilitate this physical separation. There is no
more than 8.4V between any two adjacent pins with the
exception of one instance (BOOST to BOOST–). In this
instance, the BOOST pin is pin-strapped in the applica-
tion to V– or VREG and does not need to route far from
the LTC3300-2. The package body is used to separate
the highest voltage (e.g., 25.2V) from the lowest voltage
(0V). As an example, Figure 15 shows the DC voltage on
each pin with respect to V– when six 4.2V battery cells
are connected to the LTC3300-2.
Additional “good practice” layout considerations are as
follows:
1. The VREG pin should be bypassed to the exposed pad
and to V–, each with 1µF or larger capacitors as close
to the LTC3300-2 as possible.
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
G6S—PIN 1
I6S
G5S
I5S
G4S
I4S
G3S
I3S
G2S
I2S
G1S
I1S
LTC3300-2
(EXPOSED PAD = 0V)
C5 21V
G5P 16.8V TO 25.2V
I5P 16.8V
C4 16.8V
G4P 12.6V TO 21V
I4P 12.6V
C3 12.6V
G3P 8.4V TO 16.8V
I3P 8.4V
C2 8.4V
G2P 4.2V TO 12.6V
I2P 4.2V
33002 F15
Figure 15. Typical Pin Voltages for Six 4.2V Cells
2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to
exposed pad) should be bypassed with a 1µF or larger
capacitor as close to the LTC3300-2 as possible. This
is in addition to bulk capacitance present in the power
stages.
3. Pin 21 (V–) is the ground sense for current sense resis-
tors connected to I1S-I6S and I1P (seven resistors).
Pin 21 should be Kelvined as well as possible with low
impedance traces to the ground side of these resistors
before connecting to the LTC3300-2 exposed pad.
4. Cell inputs C1 to C5 are the ground sense for current
sense resistors connected to I2P-I6P (five resistors).
These pins should be Kelvined as well as possible
with low impedance traces to the ground side of these
resistors.
5. The ground side of the maximum on-time setting resis-
tors connected to the RTONS and RTONP pins should
be Kelvined to Pin 21 (V–) before connecting to the
LTC3300-2 exposed pad.
6. Trace lengths from the LTC3300-2 gate drive outputs
(G1S-G6S and G1P-G6P) and current sense inputs
(I1S-I6S and I1P-I6P) should be as short as possible.
7. The boosted gate drive components (diode and ca-
pacitor), if used, should form a tight loop close to the
LTC3300-2 C6, BOOST+, and BOOST– pins.
8. For the external power components (transformer, FETs
and current sense resistors), it is important to keep the
area encircled by the two high speed current switching
loops (primary and secondary) as tight as possible.
This is greatly aided by having two additional bypass
capacitors local to the power circuit: one differential
cell to cell and one from the transformer secondary to
local V–.
A representative layout incorporating all of these recom-
mendations is implemented on the DC2064A demo board
for the LTC3300-1 companion product (with further ex-
planation in its accompanying demo board manual). To
accommodate the LTC3300-2, only minor modifications
to Pins 43 to 47 connections need to be made. PCB layout
files (.GRB) are also available from the factory.
36
For more information www.linear.com/LTC3300-2
33002f