LTC3300-2_15 Datasheet, PDF (24/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer

LTC3300-2
OPERATION
SERIAL PORT OPERATION
Overview
The LTC3300-2 has an SPI bus compatible serial port.
Devices can be connected in parallel, using digital isolators.
Multiple devices are uniquely identified by a part address
determined by the A0 to A4 pins.
Physical Layer
On the LTC3300-2, four pins comprise the serial interface:
CSBI, SCKI, SDI and SDO. The SDO and SDI pins may
be tied together, if desired, to form a single bidirectional
port. Five address pins (A0 to A4) set the part address.
All serial communication related pins are voltage mode
with voltage levels referenced to the V_REG and V^– supplies.
Data Link Layer
Clock Phase and Polarity: The LTC3300-2 SPI-compatible
interface is configured to operate in a system using
CPHA = 1 and CPOL = 1. Consequently, data on SDI must
be stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 8a). Similarly, on a read,
the data value on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of SCKI (Figure 8b).
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
CSBI
SCKI
SDI
MSB (CMD)
LSB (CMD)
MSB (DATA)
(8a) Transmission Format (Write)
CSBI
LSB (DATA)
SCKI
SDI
MSB (CMD)
LSB (CMD)
SDO
24
MSB (DATA)
(8b) Transmission Format (Read)
Figure 8.
For more information www.linear.com/LTC3300-2
LSB (DATA)
33002 F08
33002f