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LTC3300-2_15 Datasheet, PDF (31/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer
LTC3300-2
APPLICATIONS INFORMATION
Supplementary Voltage Regulator Drive (>40mA)
The 4.8V linear voltage regulator internal to the LTC3300-2
is capable of providing 40mA at the VREG pin. If additional
current capability is required, the VREG pin can be back-
driven by an external low cost 5V buck DC/DC regulator
C6
IOUT > 40mA
LTC3300-2
VIN
SW
L 5V
BUCK
CIN
DC/DC
RFB2
VREG
4.8V
LINEAR
VOLTAGE
REGULATOR
FB
GND
RFB1
COUT
V–
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Figure 11. Adding External Buck DC/DC for >40mA VREG Drive
powered from C6 as shown in Figure 11. The internal
regulator of the LTC3300-2 has very limited sink current
capability and will not fight the higher forced voltage.
Fault Protection
Care should always be taken when using high energy
sources such as batteries. There are numerous ways
that systems can be misconfigured when considering
the assembly and service procedures that might affect a
battery system during its useful lifespan. Table 9 shows
the various situations that should be considered when
planning protection circuitry. The first four scenarios
are to be anticipated during production and appropriate
protection is included within the LTC3300-2 device itself.
Table 9. LTC3300-2 Failure Mechanism Effect Analysis
SCENARIO
EFFECT
Top cell (C6) input connection loss to LTC3300-2. Power will come from highest connected cell
input or via data port fault current.
Bottom cell (V–) input connection loss to
LTC3300-2.
Power will come from lowest connected cell
input or via data port fault current.
Random cell (C1-C5) input connection loss to
LTC3300-2.
Power-up sequence at IC inputs/differential
input voltage overstress.
Disconnection of a harness between a sub-stack Loss of all supply connections to the IC.
of battery cells and the LTC3300-2 (in a system of
stacked groups).
Secondary winding connection loss to battery
stack.
Shorted primary winding sense resistor.
Secondary winding power FET could be
subjected to a higher voltage as bypass
capacitor charges up.
Primary winding peak current cannot be
detected to shut off primary switch.
Shorted secondary winding sense resistor.
Secondary winding peak current cannot be
detected to shut off secondary switch.
Data error (noise margin induced or otherwise)
occurs during a write command.
Incoming checksum will not agree with the
incoming message when read in by any
individual LTC3300-2 in the stack.
Data error (noise margin induced or otherwise)
occurs during a read command.
Outgoing checksum (calculated by the
LTC3300‑2) will not agree with the
outgoing message when read in by the host
microprocessor.
For more information www.linear.com/LTC3300-2
DESIGN MITIGATION
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Zener diodes across
each cell voltage input pair (within IC) limit stress.
Clamp diodes at each pin to C6 and V– (within
IC) provide alternate power path if there are other
devices (which can supply power) connected to
the LTC3300-2.
WDT pin implements a secondary winding OVP
circuit which will detect overvoltage and terminate
balancing.
Maximum ON-time set by RTONP resistor will shut
off primary switch if peak current detect doesn’t
occur.
Maximum ON-time set by RTONS resistor will
shut off secondary switch if peak current detect
doesn’t occur.
Since the CRC remainder will not be zero, the
LTC3300-2 will not execute the write command,
even if an execute command is given. All
balancers with nonzero remainders will be off.
Since the CRC remainder (calculated by the
host) will not be zero, the data cannot be trusted.
All balancers will remain in the state of the last
previously successful write.
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