LTC3300-2_15 Datasheet, PDF (26/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer

LTC3300-2
OPERATION
For nonsynchronous discharging of cell n, both the sec-
ondary winding gate drive and (zero) current sense amp
are disabled. The secondary current will conduct either
through the body diode of the secondary switch (if pres-
ent) or through a substitute Schottky diode. The primary
will only turn on again after the secondary winding Volt-
sec clamp times out. In a bidirectional application with a
secondary switch, it may be possible to achieve slightly
higher discharge efficiency by opting for nonsynchronous
discharge mode (if the gate charge savings exceed the
added diode drop losses) but the balancing current will be
less predictable because the secondary winding Volt-sec
clamp must be set longer than the expected time for the
current to hit zero in order to guarantee no current rever-
sal. In the case where a Schottky diode replaces the sec-
ondary switch, it is possible to build a undirectional
discharge-only balancing application charging an isolated
auxiliary cell as shown in Figure 16 in the Typical Applica-
tions section.
In the CTRL = 1 application of Figure 7 employing a single
transformer which can only balance one cell at a time,
any command requesting simultaneous balancing of more
than one cell will be ignored. All active balancing will be
turned off if an Execute Balance Command is subse-
quently written.
The last 4 bits of the 16-bit balance command are used
for packet error checking (PEC). The 16 bits of write data
(12-bit message plus 4-bit CRC) are input to a cyclic re-
dundancy check (CRC) block employing the International
Telecommunication Union CRC-4 standard characteristic
polynomial:
x⁴ + x + 1
In the write data, the 4-bit CRC appended to the message
must be selected such that the remainder of the CRC divi-
sion is zero. Note that the CRC bits in the Write Balance
Command are inverted. This was done so that an “all zeros”
command is invalid. The LTC3300-2 will ignore the write
data if the remainder is not zero and the internal command
holding register will be cleared which can be verified on
readback. The current balance command being executed
(from the last previously successful write) will continue,
but all active balancing will be turned off if an Execute Bal-
ance Command is subsequently written. For information
on how to calculate the CRC including an example, refer
to the Applications Information section.
Readback Balance Command
The bit mapping for Readback Balance Command is identi-
cal to that for Write Balance Command. If the command
bits program Readback Balance Command, the 16 bits of
previously written data (latched in 12-bit message plus
newly calculated 4-bit CRC) are shifted out in the same
order bitwise (MSB first) per Table 4. Only the individ-
ual LTC3300-2 in the stack with the matching address
will send out the read data. This command allows for
microprocessor verification of written commands before
executing. Note that the CRC bits in the Readback Balance
Command are also inverted. This was done so that an “all
zeros” readback is invalid.
Read Balance Status
If the command bits program Read Balance Status, 16 bits
of status data (12 bits of data plus associated 4-bit CRC)
are shifted out MSB first per Table 6. Similar to a Readback
Balance Command, the last 4 bits in each 16-bit balance
status are used for error detection. The first 12 bits of
the status are input to a cyclic redundancy check (CRC)
block employing the same characteristic polynomial used
for write commands. The LTC3300-2 will calculate and
append the appropriate 4-bit CRC to the outgoing 12‑bit
message which can then be used for microprocessor er-
Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)
Gate Gate Gate Gate Gate Gate Cells Sec Temp 0
0
Drive 1 Drive 2 Drive 3 Drive 4 Drive 5 Drive 6 Not OV Not OV OK
OK OK OK OK OK OK
(MSB)
0 CRC[3] CRC[2] CRC[1] CRC[0]
(LSB)
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33002f