LTC3300-2_15 Datasheet, PDF (32/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer

LTC3300-2
APPLICATIONS INFORMATION
Internal Protection Diodes
Each pin of the LTC3300-2 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 12. The diodes shown are conventional
silicon diodes with a forward breakdown voltage of 0.5V.
The unlabeled Zener diode structures have a reverse-
breakdown characteristic which initially breaks down at
9V then snaps back to a 7V clamping potential. The Zener
diodes labeled Z_CLAMP are higher voltage devices with an
initial reverse breakdown of 25V snapping back to 22V.
The forward voltage drop of all Zeners is 0.5V.
The internal protection diodes shown in Figure 12 are
power devices which are intended to protect against
limited-power transient voltage excursions. Given that
these voltages exceed the absolute maximum ratings of
the LTC3300-2, any sustained operation at these voltage
levels will damage the IC.
Initial Battery Connection to LTC3300-2
In addition to the above-mentioned internal protection
diodes, there are additional lower voltage/lower current
diodes across each of the six differential cell inputs (not
shown in Figure 12) which protect the LTC3300-2 during
initial installation of the battery voltages in the application.
These diodes have a breakdown voltage of 5.3V with 20kΩ
of series resistance and keep the differential cell voltages
below their absolute maximum rating during power-up
when the cell terminal currents are zero to tens of mi-
croamps. This allows the six batteries to be connected in
any random sequence without fear of an unconnected cell
input pin overvoltaging due to leakage currents acting on
its high impedance input. Differential cell-to-cell bypass
capacitors used in the application must be of the same
nominal value for full random sequence protection.
Analysis of Stack Terminal Currents in Shutdown
As given in the Electrical Characteristics table, the quiescent
current of the LTC3300-2 when not balancing is 14μA at
the C6 pin and zero at the C1 through C5 pins. All of this
14μA shows up at the V^– pin of the LTC3300-2. To the
extent that the 14μA currents match perfectly chip-to-chip
in a long series stack, the resultant stack terminal currents
in shutdown are as follows: 14μA out of the top of stack
node and 14μA into the bottom of stack node. All other
intermediate node currents are zero.
Differences Between LTC3300-2 and LTC3300-1
The LTC3300-1 employs an SPI-compatible serial interface
in which each IC in the stack communicates bidirectionally
to the ICs of the same type above and below it via currents.
There is no limit to the stack height. Large common mode
voltage differences are handled by each LTC3300-1. The
microprocessor in the BMS system communicates ONLY
with the bottom IC in the stack and subsequently all of
the ICs use the same fixed internal address.
The LTC3300-2 employs an SPI-compatible serial interface
in which each IC has a unique 5-bit pin-strapped address.
The microprocessor in the BMS system communicates
directly with every IC in the stack with common mode
voltage differences handled by digital isolators or opto-
couplers. Because of the 5-bit address, the stack height is
limited to 32 LTC3300-2 ICs or 192 cells (~800V).
There are 5 pins which have a different assignment, all of
them serial interface related.
See Table 10 for a summary of differences between
LTC3300-1 and LTC3300-2
Table 10. LTC3300-1 vs LTC3300-2 Differences
LTC3300-1
LTC3300-2
High Side Current Mode SPI Pins CSBO, SCKO,
None
SDOI
“Where Am I in The Stack?” Pins
SPI Address
V_MODE, TOS
10101 (Fixed)
None*
A₄A₃A₂A₁A₀
(Pin Strapped)
Maximum Height of Battery Stack
GND (V^–) Pin Current in
Shutdown/Suspend
Unlimited
23.5µA
32 × 6 = 192 Cells
14µA
*LTC3300-2 has V_MODE = TOS = 1 fixed internally. Each IC in the stack
thinks it is both top-of-stack and bottom-of-stack. Consequently, opto-
couplers or digital isolators are needed to communicate between the µP
and each IC.
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