LTC3300-2_15 Datasheet, PDF (25/42 Pages) Linear Technology – Addressable High Efficiency Bidirectional Multicell Battery Balancer

LTC3300-2
OPERATION
Command Byte
All communication to the LTC3300-2 takes place with CSBI
logic low. The first 8 clocked in data bits after a high-to-
low transition on CSBI represent the command byte. The
8-bit command byte is written MSB first per Table 2. The
first 5 bits must match the fixed pin-strapped address
[A4 A3 A2 A1 A0] for the individual device, or all sub-
sequent data will be ignored until CSBI transitions high
and then low again. The 6th and 7th bits program one of
four commands as shown in Table 3. The 8th bit in the
command byte must be set such that the entire 8-bit com-
mand byte has even parity. If the parity is incorrect, the
current balance command being executed (from the last
previously successful write) is terminated immediately and
all subsequent (write) data is ignored until CSBI transi-
tions high and then low again. Incorrect parity takes this
action whether or not the address matches. This thereby
provides a fast means to immediately terminate balancing-
in-progress by intentionally writing a command byte with
incorrect parity.
Table 2. Command Byte Bit Mapping
(Defaults to 0x00 in Reset State)
A4 A3 A2 A1 A0
(MSB)
CMDA CMDB
Parity Bit
(LSB)
Table 3. Command Bits
CMDA CMDB COMMUNICATION ACTION
0
0
Write Balance Command (without Executing)
0
1
Readback Balance Command
1
0
Read Balance Status
1
1
Execute Balance Command
Write Balance Command
If the command bits program Write Balance Command,
all subsequent write data must be exactly 16 bits (before
CSBI transitions high) or it will be ignored. The internal
command holding register will be cleared which can be
verified on readback. The current balance command being
executed (from the last previously successful write) will
continue, but all active balancing will be turned off if an
Execute Balance Command is subsequently written. Only
the individual LTC3300-2 in the stack with the matching
address will load in the write data. The 16-bit write balance
command is written MSB first per Table 4.
The first 12 bits of the 16-bit balance command are used
to indicate which balancer (or balancers) is active and in
which direction (charge or discharge). Each of the 6 cell
balancers is controlled by 2 bits of this data per Table 5.
The balancing algorithm for a given cell is:
Charge Cell n: Ramp up to I_PEAK in secondary winding,
ramp down to I_ZERO in primary winding. Repeat.
Discharge Cell n (Synchronous): Ramp up to Ipeak in
primary winding, ramp down to I_ZERO in secondary
winding. Repeat.
Table 5. Cell Balancer Control Bits
Dn A
Dn B
BALANCING ACTION (n = 1 to 6)
0
0
None
0
1
Discharge Cell n (Nonsynchronous)
1
0
Discharge Cell n (Synchronous)
1
1
Charge Cell n
Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)
D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A
(MSB)
D6B CRC[3] CRC[2] CRC[1] CRC[0]
(LSB)
For more information www.linear.com/LTC3300-2
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