LTC3815_15 Datasheet, PDF (31/42 Pages) Linear Technology – 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management

LTC3815
Applications Information
Design Example
As a design example, consider using the LTC3815 in an
application with the following specifications:
V_IN = 2.25V to 5.5V, V_OUT = 1.8V, I_OUT(MAX) = 6A, I_OUT(MIN)
= 200mA, f = 2MHz.
Efficiency is important at both high and low load current,
so discontinuous operation will be utilized.
First, calculate the timing resistor:
( ) ^RT
=
1.15 • 10¹¹Hz
2 • 10^{6 1.11}
=
11.7k
Next, calculate the inductor value for about 30% ripple
current at maximum V_IN:
L
=
⎛
⎝⎜
1.8V
2MHz • 2A
⎞
⎠⎟
•
⎛⎝⎜_1–
1.8V
5.5V
⎞
⎠⎟
=
0.303µH
Using a standard value of 0.3µH inductor results in a
maximum ripple current of:
ΔI_L
=
⎛
⎝⎜
1.8V ^⎞
2MHz • 0.3µH⎠⎟
•
⎛⎝⎜_1–
1.8V
5.5V
⎞
⎠⎟
=
2.02A
C_OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 150µF (or 47µF plus 100µF) ceramic capacitor is used
with a X5R or X7R dielectric.
Assuming worst-case conditions of V_IN = 2V_OUT, C_IN should
be selected for a maximum current rating of:
I_RMS
=
6A
•
1.8V
3.6V
•
⎛
⎝⎜
3.6V
1.8V
–
1^{⎞⎠⎟}
=
3A_RMS
Decoupling PV_IN with four 22µF capacitors is adequate
for most applications.
The value of R_REF can now be determined by solving the
following equation.
R_REF
=
1.8V
100µA
= 18k
A value of 18k, 0.5% will be selected for R_REF.
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
TRACK/SS. If we set minimum t_SS = 5ms, the following
equation can be solved:
C_SS
=
5µA • 5ms
1.8V
=
13.9nF
The standard value of 15nF guarantees the minimum soft-
start up time of 5ms.
Figure 10 shows the schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3815:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3815.
2. Connect the (+) terminal of the input capacitor(s), C_IN,
as close as possible to the PV_IN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance
5. Connect the remote sense pins, V_{CC_SENSE} and
V_{SS_SENSE}, directly to the point where maximum V_OUT
accuracy is desired. The two traces should be routed
as close together as possible.
For more information www.linear.com/LTC3815
3815p
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