LTC3815_15 Datasheet, PDF (26/42 Pages) Linear Technology – 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management

LTC3815
Applications Information
200μs to 25.6ms as shown in Table 4. Minimum delay of
200μs can be set by grounding the PGLIM pin and maxi-
mum delay of 25.6ms can be set by tying PGLIM to SV_IN.
The PGFD pin is sampled only at power on and at initialization
after the rising edge of RUN_MSTR, RUN_STBY or the
OPERATION register ON bit. Changes to PGFD will not
take effect until one of these events occur.
Table 4. PGFD Resistor Selection
PGFD RESISTOR
0Ω
28kΩ
46.4kΩ
64.9kΩ
84.5kΩ
113kΩ
Open or short to V_IN
PGOOD DELAY
200μs
400μs
800μs
1.6ms
3.2ms
6.4ms
25.6ms
Address Selection (ASEL pin)
The LTC3815 slave address is selected by the ASEL pin.
The upper four bits of the address are hardwired internally
to 0100 and the lower three bits are programmed by a
resistor connected between the ASEL and SGND (see
Table 5). This allows up to 7 different LTC3815’s on
a single board. The LTC3815 will also respond to the
Global Address 0x5A and the 7-bit address stored in the
MFR_RAIL_ADDRESS register.
The ASEL pin is sampled only at power on and at initialization
after the rising edge of RUN_MSTR, RUN_STBY or OP-
ERATION register ON bit. Changes to ASEL will not take
affect until one of these events occur.
Table 5. ASEL Resistor Selection
ASEL RESISTOR
0Ω
28kΩ
46.4kΩ
64.9kΩ
84.5kΩ
102kΩ
Open or short to V_IN
SLAVE ADDRESS
0100000
0100001
0100010
0100011
0100100
0100101
0100111
Margining/C_SLEW Selection/Margin Pin
Writing to the MFR_VOUT_COMMAND register via the
PMBus allows the adjustment of the V_OUT reference up to
±25% around the voltage at the REF pin. This voltage can
be adjusted in 0.1% increments by writing the appropriate
9-bit two’s complement value to the register. The MFR_
VOUT_MARGIN_HIGH and MFR_VOUT_MARGIN_LOW
register can also be used to adjust the V_OUT reference
value by selecting the desired register with the MARGIN
pin or the OPERATION command as specified in Table 6.
Table 6. V_OUT Margining with the MARGIN Pin and OPERATION
Command
OPERATION
MARGIN ^{BITS [5:4]}
PIN BIT 5 BIT 4
V_OUT REFERENCE
<0.4V X X = [1 + MFR_VOUT_MARGIN_LOW(%) ] • V_REF
>1.2V X X = [1 + MFR_VOUT_MARGIN_HIGH(%) ] • V_REF
Hi-Z 0 0 = [1 + MFR_VOUT_COMMAND(%) ] • V_REF
Hi-Z 0 1 = [1 + MFR_VOUT_MARGIN_LOW(%) ] • V_REF
Hi-Z 1 0 = [1 + MFR_VOUT_MARGIN_HIGH(%) ] • V_REF
Hi-Z 1* 1* = [1 + MFR_VOUT_COMMAND(%) ] • V_REF
* Setting both bits 4 and 5 high at the same time is illegal and will be
ignored.
Pre-loading the registers and using the MARGIN pin
provides fast margining by eliminating the latency inher-
ent to serial bus communication. Once the registers are
loaded the output voltage change is limited only by the
loop bandwidth and the slew rate capacitor (C_SLEW).
The C_SLEW pin provides slew rate limiting during reference
voltage changes. When the reference is changed by either
the MARGIN pin, OPERATION command, or writing new
values to the register, the LTC3815 counts up or down from
the current value in the register to the new value at 0.1%
per step. The step duration is set by the C_SLEW capacitor.
The slew rate during the transition is thus:
SR =
0.1
% / ms
C_SLEW (nF)+ 0.0043
If the C_SLEW pin is left open, SR defaults to 23%/ms. The
slew rate limit can be disabled if desired by tying the C_SLEW
pin to V_IN. When disabled, the reference is immediately
stepped from old value to new value in <100ns.
3815p
26
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