LTC3899_15 Datasheet, PDF (29/38 Pages) Linear Technology – 60V Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

LTC3899
Applications Information
crowbar causes huge currents to flow, that blow the fuse
to protect against a shorted top MOSFET if the short oc-
curs while the controller is operating.
A comparator monitors the buck output for overvoltage
conditions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if V_OUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
(such as DRV_CC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3899. When the
junction temperature exceeds approximately 175°C, the
overtemperature circuitry disables the DRV_CC LDO, causing
the DRV_CC supply to collapse and effectively shutting down
the entire LTC3899 chip. Once the junction temperature
drops back to the approximately 155°C, the DRV_CC LDO
turns back on. Long-term overstress (T_J > 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3899 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of controller 2’s top
MOSFET is thus 180° out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3899 can only be synchronized to an
external clock whose frequency is within range of the
LTC3899’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V. The LTC3899 is guaranteed to synchronize to an
external clock that swings up to at least 2.5V and down
to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
0V
INTV_CC
Resistor to GND
Any of the Above
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
External Clock
75kHz to 850kHz
FREQUENCY
350kHz
535kHz
50kHz to 900kHz
Phase Locked to
External Clock
For more information www.linear.com/LTC3899
3899f
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