LTC3899_15 Datasheet, PDF (22/38 Pages) Linear Technology – 60V Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

LTC3899
Applications Information
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3899: one N-channel MOSFET for the
top switch (main switch for the bucks, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the bucks).
The peak-to-peak drive levels are set by the DRV_CC volt-
age. This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
most applications depending on the programmed DRV_CC
voltage. Pay close attention to the BV_DSS specification for
the MOSFETs as well.
The LTC3899’s unique ability to adjust the gate drive level
between 5V to 10V (OPTI-DRIVE) allows an application
circuit to be precisely optimized for efficiency. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and
the input current decreases, then the efficiency has im-
proved. If there is no change in input current, then there
is no change in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance R_DS(ON), Miller capacitance C_MILLER, input
voltage and maximum output current. Miller capacitance,
C_MILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C_MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V_DS. This result is
then multiplied by the ratio of the application applied V_DS
to the gate charge curve specified V_DS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Buck Main Switch Duty Cycle = ^VOUT
V_IN
Buck Sync Switch Duty Cycle = ^{VIN − VOUT}
V_IN
Boost
Main
Switch
Duty
Cycle
=
V_OUT − V_IN
V_OUT
Boost Sync Switch Duty Cycle = ^VIN
V_OUT
The MOSFET power dissipations at maximum output
current are given by:
( ) ^{( ) P}_{MAIN_}
BUCK
=
V_OUT
V_IN
I_{OUT(MAX )}
2
1+ δ R_DS(ON) +
(V_IN
)²


I_{OUT(MAX )}
2


(R_DR
)(C_MILLER
)
•



V_DRVCC
1
− V_THMIN
+
1
V_THMIN
_(f)

( ) ^{( ) P}_{SYNC _BUCK}
=
V_IN
− V_OUT
V_IN
I_{OUT(MAX )}
2
1+ δ
R_DS(ON)
( ) _{( ) PMAIN_BOOST =}
V_OUT − V_IN
V_IN2
V_OUT
2
I_OUT(MAX) •
(1+
)δ R_DS(ON)
+


V_OUT3
V_IN




I_{OUT(MAX )}
2


•
( )( ) R_DR
C_MILLER
•



V_DRVCC
1
− V_THMIN
+
1
V_THMIN
_(f)

( ) ^{( ) P}_SYNC
_ BOOST
=
V_IN
V_OUT
I_{OUT(MAX )}
2
1+ δ
R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and
R_DR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V_THMIN is the
typical MOSFET minimum threshold voltage.
3899f
22
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