LTC3890-3 Datasheet, PDF (28/40 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

LTC3890-3
Applications Information
The equivalent R_SENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (43mV):
R_SENSE
≤
64mV
5.73A
≈
0.01Ω
Choosing 1% resistors: R_A = 25k and R_B = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R_DS(ON) = 0.035Ω/0.022Ω, C_MILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
P_MAIN
=
3.3V
22V
(^5A)²
₁₊
(^0.005)
(^50°C
–
25°C₎^
(^0.035Ω)
+
(^22V)²
5A
2
(^2.5Ω)
(^215pF)
•

5V
1
– 2.3V
+
1
2.3V
_(350kHz)
=
331mW
A short-circuit to ground will result in a folded back cur-
rent of:
I_SC
=
34mV
0.01Ω
–
1^
2


95ns ₍22V ₎
4.7µH



=
3.18A
with a typical value of R_DS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
P_SYNC = ₍3.18A₎² ₍1.125₎₍0.022Ω₎
= 250mW
which is less than under full-load conditions.
C_IN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C_OUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V_ORIPPLE = R_ESR (∆I_L) = 0.02Ω(1.45A) = 29mV_P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at C_IN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C_INTVCC must return to the combined C_OUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the C_IN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3890-3 V_FB pins’ resistive dividers connect to
the (+) terminals of C_OUT? The resistive divider must be
connected between the (+) terminal of C_OUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
28
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