LTC3890-3 Datasheet, PDF (13/40 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

LTC3890-3
Operation (Refer to the Functional Diagram)
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV_CC or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV_CC
selects 535kHz. Placing a resistor between FREQ and
SGND allows the frequency to be programmed between
50kHz and 900kHz, as shown in Figure 10.
A phase-locked loop (PLL) is available on the LTC3890-3
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3890-3’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of controller 1’s external top MOSFET to the ris-
ing edge of the synchronizing signal. Thus, the turn-on
of controller 2’s external top MOSFET is 180 degrees out
of phase to the rising edge of the external clock source.
The VCO input voltage is prebiased to the operating
frequency set by the FREQ pin before the external clock
is applied. A resistor connected between the FREQ pin
and SGND can prebias VCO’s input voltage to the desired
frequency. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is
from approximately 55kHz to 1MHz, with a guarantee
to be between 75kHz and 850kHz. In other words, the
LTC3890-3’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE pin
are 1.6V (rising) and 1.1V (falling). When synchronized to
an external clock using the PLLIN/MODE pin, the LTC3890-3
operates in pulse-skipping mode at light loads.
Power Good (PGOOD1 Pin)
The PGOOD1 pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD1 pin low when the corresponding V_FB1 pin volt-
age is not within ±10% of the 0.8V reference voltage. The
PGOOD1 pin is also pulled low when the corresponding
RUN1 pin is low (shut down). When the V_FB1 pin voltage
is within the ±10% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source no greater than 6V.
Theory and Benefits of 2-Phase Operation
Why the need for 2-phase operation? Up until the 2‑phase
family, constant-frequency dual switching regulators
operated both channels in phase (i.e., single phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dual
switching regulator are operated 180 degrees out-of-phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
For more information www.linear.com/3890-3
38903f
13