LTC3890-3 Datasheet, PDF(27/40 Page) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

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LTC3890-3 Datasheet, PDF (27/40 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

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LTC3890-3

Applications Information

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1Âµs to 10Âµs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

and is the filtered and compensated control loop response.

The gain of the loop will be increased by increasing RC

and the bandwidth of the loop will be increased by de-

creasing CC. If RC is increased by the same factor that CC

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual overall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1ÂµF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUTâ, causing a rapid drop in VOUTâ. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 â¢ CLOAD. Thus a 10ÂµF capacitor would

require a 250Âµs rise time, limiting the charging current

to about 200mA.

Design Example

As a design example for one channel, assume VIN =

12V(nominal), VIN = 22V (max), VOUT = 3.3V, IMAX = 5A,

VSENSE(MAX) = 75mV and f = 350kHz.

The inductance value is chosen first based on a 30% ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

âIL

VOUT

(f)(L)

ï£«

ï£ï£¬ï£¬1

VOUT

VIN(NOM)

ï£¶

ï£¸ï£·ï£·

A 4.7ÂµH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.73A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

maximum VIN:

tON(MIN)

VOUT

VIN(MAX) (f)

3.3V

22V (350kHz)

429ns

For more information www.linear.com/3890-3

38903f

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