LTC3866 Datasheet, PDF (28/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

LTC3866
Applications Information
2. Place the feedback divider between the + and – termi-
nals of C_OUT. Route DIFFP and DIFFN with minimum
PC trace spacing from the IC to the feedback divider.
3. Are the SNSD⁺, SNSA⁺ and SNS^– printed circuit traces
routed together with minimum PC trace spacing? The
filter capacitors between SNSD⁺, SNSA⁺ and SNS^–
should be as close as possible to the pins of the IC.
Connect the SNSD⁺ and SNSA⁺ pins to the filter resistors
as illustrated in Figure 3.
4. Do the (+) plates of C_IN connect to the drain of the
topside MOSFET as closely as possible? This capacitor
provides the pulsed current to the MOSFET.
5. Keep the switching nodes, SW, BOOST and TG away
from sensitive small-signal nodes (SNSD⁺, SNSA⁺,
SNS^–, DIFFP, DIFFN, V_FB). Ideally the SW, BOOST and
TG printed circuit traces should be routed away and
separated from the IC and especially the quiet side of
the IC. Separate the high dv/dt traces from sensitive
small-signal nodes with ground traces or ground planes.
6. Use a low impedance source such as a logic gate to
drive the MODE/PLLIN pin and keep the lead as short
as possible.
7. The 47pF to 330pF ceramic capacitor between the I_TH
pin and signal ground should be placed as close as
possible to the IC. Figure 14 illustrates all branch cur-
rents in a switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a com-
mon ground path with any switched current paths. The
left half of the circuit gives rise to the noise generated
by a switching regulator. The ground terminations of
the synchronous MOSFET and Schottky diode should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP^® compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
28
8. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C_INTVCC must return to the combined C_OUT (–) ter-
minals. The V_FB and ITH traces should be as short as
possible. The path formed by the top N-channel MOS-
FET, Schottky diode and the C_IN capacitor should have
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
9. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
Design Example
As a design example of the front page circuit for a single
channel high current regulator, assume V_IN = 12V(nominal),
V_IN = 20V(maximum), V_OUT = 1.5V, I_MAX = 30A, and
f = 400kHz (see front page schematic).
The regulated output voltage is determined by:
V_OUT
=
0.6V
•
⎛
⎜¹⁺
⎝
R_B
R_A
⎞
⎟
⎠
Using a 20k 1% resistor from the V_FB node to ground,
the top feedback resistor is (to the nearest 1% standard
value) 30.1k.
The frequency is set by biasing the FREQ pin to 1V (see
Figure 12).
The inductance value is based on a 35% maximum ripple
current assumption (10.5A). The highest value of ripple
current occurs at the maximum input voltage:
L
=
f
•
V_OUT
∆I_{L(MAX )}
⎛
⎝⎜⎜^1−
V_OUT
V_{IN (MAX )}
⎞
⎠⎟⎟
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