LTC3866 Datasheet, PDF(27/36 Page) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

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LTC3866 Datasheet, PDF (27/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

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LTC3866

Applications Information

adequate starting point for most applications. The ITH series

RC-CC filter sets the dominant pole-zero loop compensation.

The values can be modified slightly (from 0.5 to 2 times

their suggested values) to optimize transient response

once the final PC layout is done and the particular output

capacitor type and value have been determined. The output

capacitors need to be selected because the various types

and values determine the loop gain and phase. An output

current pulse of 20% to 80% of full-load current having a

rise time of 1Âµs to 10Âµs will produce output voltage and

ITH pin waveforms that will give a sense of the overall

loop stability without breaking the feedback loop. Placing

a power MOSFET directly across the output capacitor and

driving the gate with an appropriate signal generator is a

practical way to produce a realistic load step condition. The

initial output voltage step resulting from the step change

in output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

phase margin. This is why it is better to look at the ITH

pin signal which is in the feedback loop and is the filtered

and compensated control loop response. The gain of the

loop will be increased by increasing RC and the bandwidth

of the loop will be increased by decreasing CC. If RC is

increased by the same factor that CC is decreased, the

zero frequency will be kept the same, thereby keeping the

phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and

will demonstrate the actual overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1ÂµF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUTâ, causing a rapid drop in VOUTâ. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 â¢ CLOAD. Thus a 10ÂµF capacitor would

require a 250Âµs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 14. Check the following in the

PC layout:

1. The INTVCC decoupling capacitor should be placed

immediately adjacent to the IC between the INTVCC pin

and PGND plane. A 1ÂµF ceramic capacitor of the X7R

or X5R type is small enough to fit very close to the IC

to minimize the ill effects of the large current pulses

drawn to drive the bottom MOSFETs. An additional

4.7ÂµF to 10ÂµF of ceramic, tantalum or other very low

ESR capacitance is recommended in order to keep the

internal IC supply quiet.

VIN

VOUT

SW2

DCR

RIN +

CIN

SW1

COUT

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

Figure 14. Branch Current Waveforms

3866 F14

3866fa

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