LTC3866 Datasheet, PDF (25/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

LTC3866
Applications Information
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
2.5
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Figure 12. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
2.4V 5.5V
10µA
R_SET
MODE/PLLIN
EXTERNAL
OSCILLATOR
DIGITAL _SYNC
PHASE/
FREQUENCY
DETECTOR
FREQ
VCO
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Figure 13. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
Typically, the external clock (on the MODE/PLLIN pin) input
high threshold is 1.6V, while the input low threshold is 1V.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3866 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t_ON(MIN)
<
V_OUT
V_{IN (}f₎
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the voltage ripple and current ripple will increase. The
minimum on-time for the LTC3866 is approximately 90ns,
with good PCB layout, minimum 30% inductor current
ripple and at least 2mV ripple on the current sense signal.
The minimum on-time can be affected by PCB switch-
ing noise in the voltage and current loop. As the peak
sense voltage decreases the minimum on-time gradually
increases to about 110ns. This is of particular concern in
forced continuous applications with low ripple current at
light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3866 circuits: 1) IC V_IN current, 2)
INTV_CC regulator current, 3) I²R losses, 4) topside MOSFET
transition losses.
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