LTC3866 Datasheet, PDF (13/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

LTC3866
Operation
If the MODE/PLLIN pin is not being driven by an external
clock source, the FREQ pin can be used to program the
controller’s operating frequency from 250kHz to 770kHz.
There is a precision 10µA current flowing out of the FREQ
pin so that the user can program the controller’s switch-
ing frequency with a single resistor to SGND. A curve
is provided later in the Applications Information section
showing the relationship between the voltage on the FREQ
pin and switching frequency.
A phase-locked loop (PLL) is available on the LTC3866
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The PLL
loop filter network is integrated inside the LTC3866. The
phase‑locked loop is capable of locking any frequency
within the range of 250kHz to 770kHz. The frequency setting
resistor should always be present to set the controller’s
initial switching frequency before locking to the external
clock. The controller operates in forced continuous mode
when it is synchronized.
Sensing the Output Voltage with a
Differential Amplifier
The LTC3866 includes a low offset, high input impedance,
unity-gain, high bandwidth differential amplifier for ap-
plications that require true remote sensing. Sensing the
load across the load capacitors directly greatly benefits
regulation in high current, low voltage applications, where
board interconnection losses can be a significant portion
of the total error budget. Connect DIFFP to the output load,
and DIFFN to the load ground. See Figure 1.
V_OUT
C_OUT
8 ^DIFFP +
DIFFAMP
7 ^DIFFN –
LTC3866
DIFFOUT
6
V_FB 5
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Figure 1. Differential Amplifier Connection
The LTC3866 differential amplifier has a typical output slew
rate of 2V/µs. The amplifier is configured for unity gain,
meaning that the difference between DIFFP and DIFFN is
translated to DIFFOUT, relative to SGND.
Care should be taken to route the DIFFP and DIFFN PCB
traces parallel to each other all the way to the remote sens-
ing points on the board. In addition, avoid routing these
sensitive traces near any high speed switching nodes in
the circuit. Ideally, the DIFFP and DIFFN traces should be
shielded by a low impedance ground plane to maintain
signal integrity.
Power Good (PGOOD Pin)
The PGOOD pin is connected to the open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the V_FB pin voltage is not
within ±10% of the 0.6V reference voltage. The PGOOD
pin is also pulled low when the RUN pin is below 1.14V or
when the LTC3866 is in the soft-start or tracking up phase.
When the V_FB pin voltage is within the ±10% regulation
window, the MOSFET is turned off and the pin is allowed
to be pulled up by an external resistor to a source of up
to 6V. The PGOOD pin will flag power good immediately
when the V_FB pin is within the regulation window. However,
there is an internal 20µs power-bad mask when the V_FB
goes out of the window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Undervoltage Lockout
The LTC3866 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTV_CC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV_CC is below
3.75V. To prevent oscillation when there is a disturbance
on the INTV_CC, the UVLO comparator has 600mV of preci-
sion hysteresis.
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