LTC3866 Datasheet, PDF (24/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

LTC3866
Applications Information
as shown in Figure 11. The regulated output voltage is
determined by:
V_OUT
=
0.6V
•
⎛
⎜¹⁺
⎝
R_B
R_A
⎞
⎟
⎠
To improve the frequency response, a feedforward ca-
pacitor, C_FF , may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
To minimize the effect of the voltage drop caused by high
current flowing through board conductance; connect DIFFN
and DIFFP sense lines close to the ground and the load
output respectively.
DIFFOUT
LTC3866
V_FB
R_B
C_FF
R_A
3866 F11
Figure 11. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3866 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maxi-
mum value. Foldback current limiting is disabled during
the soft-start or tracking up using the TK/SS pin. It is not
disabled for internal soft-start. Under short-circuit condi-
tions with very low duty cycles, the LTC3866 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short circuit ripple current is determined by the minimum
on-time t_ON(MIN) of the LTC3866 (≈90ns), the input voltage
and inductor value:
∆I_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
⎛
⎜
⎝
1
/3
V_{SENSE(MAX )}
R_SENSE
–
1
2
∆I_L(SC)
⎞
⎟
⎠
After a short, or while starting with internal soft-start, make
sure that the load current takes the folded-back current
limit into account.
Phase-Locked Loop and Frequency Synchronization
The LTC3866 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. There is a precision 10µA current flowing
out of the FREQ pin. This allows the user to use a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between the FREQ pin and the integrated
PLL filter network is on, allowing the filter network to be
pre-charged to the same voltage as the FREQ pin. The
relationship between the voltage on the FREQ pin and
operating frequency is shown in Figure 12 and specified
in the Electrical Characteristics table. If an external clock
is detected on the MODE/PLLIN pin, the internal switch
mentioned above turns off and isolates the influence of the
FREQ pin. Note that the LTC3866 can only be synchronized
to an external clock whose frequency is within range of
the LTC3866’s internal VCO. This is guaranteed to be
between 250kHz and 770kHz. A simplified block diagram
is shown in Figure 13.
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