LTC3866 Datasheet, PDF (18/36 Pages) Linear Technology – Current Mode Synchronous Controller for Sub Milliohm DCR Sensing

LTC3866
Applications Information
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, f_OSC, directly determine
the inductor’s peak-to-peak ripple current:
I_RIPPLE
=
V_OUT
V_IN
⎛
⎜
⎝
V_IN – V_OUT
f_OSC • L
⎞
⎟
⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I_OUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L ≥ ^{VIN – VOUT} • ^VOUT
f_OSC • I_RIPPLE V_IN
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs need to be selected:
One N-channel MOSFET for the top (main) switch and one
or more N‑channel MOSFET(s) for the bottom (synchro-
nous) switch. The number, type and on-resistance of all
MOSFETs selected take into account the voltage step-down
ratio as well as the actual position (main or synchronous)
in which the MOSFET will be used. A much smaller and
much lower input capacitance MOSFET should be used
for the top MOSFET in applications that have an output
voltage that is less than one-third of the input voltage. In
applications where V_IN >> V_OUT , the top MOSFETs’ on-
resistance is normally less important for overall efficiency
than its input capacitance at operating frequencies above
300kHz. MOSFET manufacturers have designed special
purpose devices that provide reasonably low on-resistance
with significantly reduced input capacitance for the main
switch application in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
internal regulator voltage, V_INTVCC, requiring the use of
logic-level threshold MOSFETs in most applications. Pay
close attention to the BV_DSS specification for the MOSFETs
as well; many of the logic-level MOSFETs are limited to
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, R_DS(ON), input capacitance,
input voltage and maximum output current. MOSFET input
capacitance is a combination of several components but
can be taken from the typical gate charge  curve included
on most data sheets (Figure 7). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
3866fa
18