LTC3729L-6 Datasheet, PDF (24/28 Pages) Linear Technology – PolyPhase, Synchronous Step-Down Switching Regulator

LTC3729L-6
APPLICATIO S I FOR ATIO
8) Minimize the capacitive load on the CLKOUT pin to
minimize excess phase shift. Buffer if necessary with an
NPN emitter follower.
9) The I_TH pin capacitor should be as close to the I_TH pin
as possible.
The diagram in Figure 9 illustrates all branch currents in a
2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regula-
tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the bottom plate(s)
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the bottom plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur-
rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
SW1
D1
L1
R_SENSE1
V_IN
R_IN
+
C_IN
V_OUT
+ ^COUT
R_L
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
SW2
D2
L2
R_SENSE2
24
Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
3729L-6 F09
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