LTC3729L-6 Datasheet, PDF(23/28 Page) Linear Technology – PolyPhase, Synchronous Step-Down Switching Regulator

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LTC3729L-6 Datasheet, PDF (23/28 Pages) Linear Technology – PolyPhase, Synchronous Step-Down Switching Regulator

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LTC3729L-6

APPLICATIO S I FOR ATIO

The worst-case power disipated by the synchronous

MOSFET under short-circuit conditions at elevated ambi-

ent temperature and estimated 50Â°C junction temperature

rise is:

PSYNC

5.5V â 1.8V

5.5V

(5.28A)2(1.25)(0.008â¦)

= 188mW

which is much less than normal, full-load conditions.

Incidentally, since the load no longer dissipates power in

the shorted condition, total system power dissipation is

decreased by over 99%.

The duty cycles when the peak RMS input current occurs

is at D = 0.25 and D = 0.75 according to Figure 4. Calculate

the worst-case required RMS input current rating at the

input voltage, which is 5.5V, that provides a duty cycle

nearest to the peak.

From Figure 4, CIN will require an RMS current rating of:

CINrequiredIRMS = (20A)(0.23)

= 4.6ARMS

The output capacitor ripple current is calculated by using

the inductor ripple already calculated for each inductor

and multiplying by the factor obtained from Figureâ£ 3 along

with the calculated duty factor. The output ripple in con-

tinuous mode will be highest at the maximum input

voltage. From Figure 3, the maximum output current ripple

is:

âICOUT

VOUT

(0.34)

âICOUTMAX

1.8(0.34)

(260kHz)(2ÂµH)

1.2A

Note that the PolyPhase technique will have its maximum

benefit for input and output ripple currents when the

number of phases times the output voltage is approxi-

mately equal to or greater than the input voltage.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3729L-6. These items are also illustrated graphically

in the layout diagram of Figureâ£ 11. Check the following in

your layout:

1) Are the signal and power grounds segregated? The

LTC3729L-6 signal ground pin should return to the (â)

plate of COUT separately. The power ground returns to the

sources of the bottom N-channel MOSFETs, anodes of the

Schottky diodes, and (â) plates of CIN, which should have

as short lead lengths as possible.

2) Does the LTC3729L-6 VOS+ pin connect to the (+)

plate(s) of COUT? Does the LTC3729L-6 VOSâ pin connect

to the (â) plate(s) of COUT? The resistive divider R1, R2

must be connected between the VDIFFOUT and signal

ground and any feedforward capacitor across R1 should

be as close as possible to the LTC3729L-6.

3) Are the SENSE â and SENSE + leads routed together with

minimum PC trace spacing? The filter capacitors between

SENSE + and SENSEâ pin pairs should be as close as

possible to the LTC3729L-6. Ensure accurate current

sensing with Kelvin connections to the sense resistors.

4) Do the (+) plates of CIN connect to the drains of the

topside MOSFETs as closely as possible? This capacitor

provides the AC current to the MOSFETs. Keep the input

current path formed by the input capacitor, top and bottom

MOSFETs, and the Schottky diode on the same side of the

PC board in a tight loop to minimize conducted and

radiated EMI.

5) Is the INTVCC 1ÂµF ceramic decoupling capacitor con-

nected closely between INTVCC and the power ground pin?

This capacitor carries the MOSFET driver peak currents. A

small value is used to allow placement immediately adja-

cent to the IC.

6) Keep the switching nodes, SW1 (SW2), TG1, TG2 away

from sensitive small-signal nodes. Ideally the switch

nodes should be placed at the furthest point from the

LTC3729L-6.

7) Use a low impedance source such as a logic gate to drive

the PLLIN pin and keep the lead as short as possible.

sn3729l6 3729l6fs

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